An efficient video data security mechanism based on RP-AES

(Cryptography Advanced Encryption Standard (AES) for File Document Encryption). Advanced Encryption Standard (AES) is a cryptographic algorithms as a standard symmetric key encryption algorithm that used in current time. AES 128 has 1 blok plaintext with 128 bit sized, where in the process of cryptographic algorithms, first the plaintext is converted into hexadecimal-sized 4 x 4 matrices called the state, where each element of state has 1 byte size. The process of encryption on AES is the transformation towards the state repeatedly in the 10th round. Each round of AES requires one key result of the key generation using 2 basic transformation, i.e. substitution and transformation. AES encryption using 4 transformation by the following sequence: subbytes, shiftrows, mixcolumns, and addroundkey. On the other hand, the process of decryption is using the inverse of all the basic transformation of AES algorithm, except addroundkey. Therefore, the sequence of transformation on the decription is invshiftrows, invsubbytes, invmixcolumns, and addroundkey. In the data text, the encryption process is initiated with convertion the data text into ASCII code in hexadecimal numbers that are molded into the matrix 4 x 4 bytes. Next, do some basic transformation such as subbytes, shiftrows, mixcolumns, and addroundkey. However, when performing the transformation, the processed data on every trasformation is in the form of binary data obtained from the hexadecimal matrix. AES 128 bit cryptography have room 2128 keys which is a tremendous value and is considered secure to use to avoid the brute force attack.

The rapid The main problem in the misuse of data used in crime is the result of a lack of file security. This study proposes a data security method to protect document files using the Advanced Encryption Standard (AES) algorithm combined with the Vigenere Cipher. This research carried out 2 processes, namely the encryption process and the decryption process. The encryption process will be carried out by the AES algorithm and then encrypted again with the Vigenere Cipher algorithm. The experiments show that the proposed method can encrypt files properly, where there are changes in the value of the document file and the encrypted file cannot be opened and the description results do not cause changes to the original file. The results of this study are that the system is able to work properly so as to produce file encryption and decryption using the AES method combined with the Vigenere Cipher. In document files, the largest difference in encryption and decryption time is 8 seconds, while in image files the difference in encryption and decryption time is 17 seconds. This longest time difference is generated by large files.

In the rapid evolving digital landscape, the imperative to ensure data security has never been more crucial. This paper addresses the pressing challenges in data security by introducing a file encryption management system, leveraging a modified advanced encryption standard (AES) algorithm with reduced round iterations and bit permutation. This system aims to comprehensively secure various file types, providing a dependable solution for file exchange. Our findings reveal substantial improvements in both encryption and decryption processes using the reduced-round permutation-based AES (RRPBA). The adapted algorithm demonstrates a significant 38.8% acceleration in encryption time and a remarkable 44.86% improvement in decryption time, positioning it as a pivotal component for efficient file operations within the management system. Moreover, the throughput assessments showcase a remarkable 33.73% improvement in encryption and 23.72% in decryption, outperforming the original AES, emphasizing the algorithm's superior computational effectiveness, signaling positive implications for future high-performance applications. In conclusion, the study not only addresses critical security challenges but also presents a viable solution with tangible speed advantages for file encryption and decryption processes within digital file management systems.

The RC-5 algorithm is an algorithm with the encryption method using the symmetric method and processing in the form of a cipher block, the same keywords are used for the encryption and decryption processes. The testing and analysis phase consists of a). Testing the execution time of the key generation process (set up key) b). Testing the success of the encryption and decryption process on the client-server integration method c). Testing the success of the encryption and decryption process using the file operation method d). Comparison of overhead/file size before and after passing through the system. The testing phase and execution time analysis are carried out when using the file operation method where the test will be divided into 3 parts, namely the execution time for the key setup process, the encryption process, and the decryption process. Testing the success of the encryption and decryption process on the client-server integration method is divided into 2 parts, namely testing the encryption process and the decryption process. In testing the encryption process, the characters that will be sent to the server will be encrypted first with a key to becoming a ciphertext in the form of integer data. The test results obtained are 1). The execution time for key generation (set up key) is very fast, around 9-10 ns. 2). In the encryption and decryption process, the execution time depends on the size of the plaintext file. The larger the plaintext file size, the longer the execution time. Where for a file with a size of 1 kb requires an execution time of 50.6 ms in the encryption process. 3). There is no difference between the size of the file before entering encryption and after decryption. Where for files with a size of 500 bytes before entering the encryption process, a file of 500 bytes will be generated from the decryption process.

Fault-based side channel cryptanalysis is a very effective cryptanalytic technique against symmetric and asymmetric encryption algorithms. Attackers can induce errors during the encryption or decryption process in order to collect information concerning secret information, such as cryptographic keys. In recent years, the security of the Advanced Encryption Standard (AES) against fault analysis attacks has received considerable attention. While FPGAs are becoming increasingly popular for cryptographic applications, there are only few articles that assess their vulnerability to such attacks only a small number of experiments can be found in the literature on the actual possibility to apply such attacks to FPGAs. The purpose of this paper is to describe a practical and successful implementation of the attack and to provide strong evidence that fault induction is a serious threat against realizations of the AESon FPGAs without effective countermeasure. The results obtained in this paper can serve to design a more secure FPGA implementation of the AES.

Small embedded systems, such as using a 16-bit CPU, are required to connect to the Internet. In addition, the systems are required to support encrypted communication. We develop a ubiquitous platform which supports Internet Protocol version 6 (IPv6) and IP Security (IPSec). This paper describes realization of Advanced Encryption Standard (AES) processing controlled by an original compact CPU core for small embedded systems. AES encryption and decryption processing requires CPU capability. AES accelerators for a Field Programmable Gate Array (FPGA) perform high speed execution, furthermore they require the resources of an FPGA. In order to conserve the resources of the FPGA, the basic operations of AES, SubBytes, ShiftRows and MixColumns transformation, are incorporated in each hardware module. The modules are controlled by the original compact CPU core. Moreover, the CPU core is designed for small embedded systems. The CPU core is able to support only instructions used in application software. Using the CPU core, AES processing is accomplished conserving FPGA resources, and is simply designed.

A new LabVIEW simulation design was applied to provide a comparison study among several types of the most common symmetric and asymmetric encryption algorithms. Also, the comparison with advanced encryption package program was made. The results showed that the new LabVIEW simulation design had advantages in several points, where the evaluated time required for the encryption and decryption processes will be lesser than it values using advanced encryption package program.In this work, the symmetric encryption algorithms were used: AES (Advanced Encryption Standard), DES (Data Encryption Standard), 3DES (Triple Data Encryption Standard) and RC2 (Rivest Cipher) algorithms, while the asymmetric encryption algorithm used was the RSA (Rivest-Shamir-Aldeman) algorithm. The comparison had been achieved using different sizes of text files with different key sizes. The final results proved that the LabVIEW simulation design is better than the Advanced Encryption Package because it increased the algorithm’s performance by 65% in terms of speed and throughput, and for the algorithms’ comparison, the final results showed the effectiveness of AES algorithm over the other algorithms in terms of speed and throughput for the encryption and decryption processes.

Nowadays, a large number of digital data are transmitted worldwide using wireless communications. Therefore, data security is a significant task in communication to prevent cybercrimes and avoid information loss. The Advanced Encryption Standard (AES) is a highly efficient secure mechanism that outperforms other symmetric key cryptographic algorithms using message secrecy. However, AES is efficient in terms of software and hardware implementation, and numerous modifications are done in the conventional AES architecture to improve the performance. This research article proposes a significant modification to the AES architecture’s key expansion section to increase the speed of producing subkeys. The fork–join model of key expansion (FJMKE) architecture is developed to improve the speed of the subkey generation process, whereas the hardware resources of AES are minimized by avoiding the frequent computation of secret keys. The AES-FJMKE architecture generates all of the required subkeys in less than half the time required by the conventional architecture. The proposed AES-FJMKE architecture is designed and simulated using the Xilinx ISE 5.1 software. The Field Programmable Gate Arrays (FPGAs) behaviour of the AES-FJMKE architecture is analysed by means of performance count for hardware resources, delay, and operating frequency. The existing AES architectures such as typical AES, AES-PNSG, AES-AT, AES-BE, ISAES, AES-RS, and AES-MPPRM are used to evaluate the efficiency of AES-FJMKE. The AES-FJMKE implemented using Spartan 6 FPGA used fewer slices (i.e., 76) than the AES-RS.

Based on the different representations of the finite field GF(256), there are different Advanced Encryption Standard (AES) implementations, which is called dual ciphers. They have the same encryption process as AES, but with parameters modified. The research of dual ciphers initially aims to find more efficient AES implementations, and later it is found that they can be used to resist side-channel attacks and for white box ciphers. In this paper, based on the rotation of columns, we propose new AES dual ciphers, which use AES directly, but with the input matrices (plaintexts and keys) and output matrix rotated. The key expansion algorithm only needs some change on the computation sequence. Because of these features, there is almost no extra cost in implementing dual ciphers and it is easy for new dual ciphers to work with other side-channel protection methods to protect AES in more dimensions.

Mobile ad hoc network (MANET) is a group of mobile nodes that communicates with each other without any supporting infrastructure. These networks have some unique features such as dynamic mobility, open nature, lack of infrastructure, limited physical security and they are vulnerable to several security threats. Malicious node can drop all or partial received packets instead of forwarding them to the next hop through the path. In order to find the malicious nodes, an initial transmission is made between the source and destination nodes. Using fuzzy rules, the trust value of each node is computed and it varies from 0 to 1. A common threshold value is set for each node and by using this threshold value, every node in the network can be identified as either a malicious node or a regular node. After identifying the malicious nodes, these nodes are eliminated by muting the power to off state. As the malicious nodes are eliminated between source and destination nodes, source node can select another trusted path to its destination
 node. For security and authentication of routing information, hybrid cryptography is employed, using advanced encryption standard (AES) and elliptic curve cryptography (ECC) algorithms. AES algorithm is used as symmetric algorithm to encrypt the routing information and ECC algorithm is used as asymmetric algorithm to encrypt the public key. During encryption, the original plain text is converted into cipher text with encrypted public key and similarly during decryption cipher text is converted into original plain text with decrypted private keys. So the proposed method involves both AES and ECC algorithms which provides security mechanism as efficient and sufficient one. The experimental simulations are carried for the proposed model using network simulator 2 (NS-2) for Throughput, Delay, Packet delivery ratio, Packet overhead and Packet drop.

In this paper, we propose area-efficient Advanced Encryption Standard (AES) processor designs by applying a new common-subexpression-elimination (CSE) algorithm to the subfunctions that realize the various transformations in AES encryption and decryption. The first category of subfunctions is derived by combining adjacent transformations in each AES round into a new transformation. The other category of subfunctions is from the integrated transformations in the AES encryption and decryption process with shared common operations. Then the proposed bit-level CSE algorithm reduces further the area cost of realizing the subfunctions by extracting the common factors in the bit-level expressions of these subfunctions. The separate area-reduction effects of combinations, integrations, and CSE optimization mentioned above are analyzed in order to examine the efficiency of each technique. Cell-based implementation results show that the proposed AES designs can achieve am area reduction rate of about 20% compared with Synopsys optimization results.

Documents are valuable assets that often contain important information, including employee personal data, and are vulnerable to security threats such as theft and alteration by unauthorized parties. This research aims to develop an Android-based document security application that combines the Advanced Encryption Standard (AES) algorithm and cloud computing technology. This type of research is developed using the System Development Life Cycle (SDLC) model, which involves requirements analysis, design, coding, and testing. At the needs analysis stage, focus is given to employee data that needs to be secured. System design includes data structure, system structure, and user interface (UI). System design includes use case elements, class diagrams, and application architecture. Coding was done using Flutter as the user interface, Laravel as the backend, and MySQL as the database. System testing uses black box testing. Our test results show that the data security application is successful in carrying out the data encryption and decryption processes. Compared to previous web and desktop-based developments, this application provides a more adaptive solution to high mobility in the work environment. Cloud computing integration provides flexibility in data access, and the use of the Android platform significantly increases user mobility.

Big-data storage poses significant challenges to anonymization of sensitive information against data sniffing. Not only will the encryption bandwidth be limited by the I/O traffic, the transfer of data between the processor and the memory will also expose the input-output mapping of intermediate computations on I/O channels that are susceptible to semi-invasive and non-invasive attacks. Limited by the simplistic cell-level logic, existing logic-in-memory computing architectures are incapable of performing the complete encryption process within the memory at reasonable throughput and energy efficiency. In this paper, a block-level in-memory architecture for advanced encryption standard (AES) is proposed. The proposed technique, called DW-AES, maps all AES operations directly to the domain-wall nanowires. The entire encryption process can be completed within a homogeneous, high-density, and standby-power-free non-volatile spintronic-based memory array without exposing the intermediate results to external I/O interface. Domain-wall nanowire-based pipelining and multi-issue pipelining methods are also proposed to increase the throughput of the baseline DW-AES with an insignificant area overhead and negligible difference on leakage power and energy consumption. The experimental results show that DW-AES can reduce the leakage power and area by the orders of magnitude compared with existing CMOS ASIC accelerators. It has an energy efficiency of 22 pJ/b, which is $5\times $ and $3\times $ better than the CMOS ASIC and memristive CMOL-based implementations, respectively. Under the same area budget, the proposed DW-AES achieves $4.6\times $ higher throughput than the latest CMOS ASIC AES with similar power consumption. The throughput improvement increases to $11\times $ for pipelined DW-AES at the expense of doubling the power consumption.

In a symmetric cryptosystem, the key used for encrypting a message is the same as the key used for decrypting a message. Although this does place a burden of proper key management and security on the users of such a cryptosystem, there have been two major cryptosystems, the Digital Encryption Standard (DES) and the Advanced Encryption Standard (AES), promulgated by the National Institute of Standards and Technology. DES was controversial due to the manner in which it was promulgated, and it has largely been superseded by the AES, about which almost no controversy exists. AES is currently in wide use in part because it is the NIST standard and in part because its design makes it fast and usable on a variety of platforms with different computational capabilities. This chapter covers the technical aspects of AES. Code for AES and test results appear in Appendix B so that code testing can be done and the encryption process observed.

Hardware Trojans pose a significant threat to the security and integrity of cryptographic systems, particularly in Advanced Encryption Standard (AES) implementations, which are widely used in securing sensitive data. These malicious modifications to integrated circuits (ICs) can compromise the confidentiality and reliability of AES cryptographic operations by introducing covert backdoors, information leakage channels, or functional disruptions. Hardware Trojans are typically designed to evade detection during design-time validation and post-manufacturing testing, often activating only under specific triggers such as rare input patterns or environmental conditions. In AES systems, Trojans can manipulate the encryption process by leaking secret keys through side-channel information such as power consumption, timing variations, or electromagnetic emissions. Some Trojans directly alter the encryption algorithm, weakening the cryptographic strength and rendering encrypted data vulnerable to attacks. Attackers may also embed Trojans at the Register Transfer Level (RTL) or gate-level design, leveraging the inherent complexity of AES circuits to conceal their presence. Detection and mitigation of hardware Trojans in AES implementations are challenging due to their stealthy nature. Techniques such as side-channel analysis, functional verification, and static code analysis have been developed, but sophisticated Trojans often bypass these methods. Advanced countermeasures include runtime monitoring, hardware obfuscation, and Trojan-resilient design methodologies. This paper explores the implications of hardware Trojans in AES cryptographic systems, analysing their design, potential attack vectors, and impacts on data security. Furthermore, it discusses state-of-the-art detection and prevention techniques, highlighting gaps and future research directions. Given the critical role of AES in securing financial, military, and consumer data, addressing the hardware Trojan threat is paramount to ensuring trust in cryptographic hardware and safeguarding against adversarial exploitation.