An efficient VLSI architecture of sub-pixel interpolator for AVS encoder

Abstract

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Interpolation is the main bottleneck in AVS real-time high definition video encoder for its high memory bandwidth and large calculation complexity caused by the new coding features of variable block size and 4-tap filter. In this paper, an efficient VLSI architecture of interpolation supporting AVS Baseline@L4 is presented. Vertical redundant data reuse, horizontal redundant data reuse and sub-pixel data reuse schemes are presented to reduce memory bandwidth and processing cycle. The separated 1-D interpolation filters are used to improve throughput and hardware utilization. The proposed design is implemented on the Vertex4 XC4VLX200 field programmable gate array with operating frequency of 150 MHz and can support 1080p (1920 times 1080) 30 fps AVS real-time encoder. It is a useful intellectual property design for real-time high definition video application.