An extended analysis of memory hierarchies for efficient implementations of image processing applications

This paper studied the characteristics of time and energy consumption of gear hobbing in batch production of small modulus gear. A method of integrating design of experiment, response surface method and multi-objective salp swarm algorithm (DOE/RSM/MMSA) is proposed for the complex optimization of machining parameters (namely hob rotation speed, cutting feed and depth of cut) in gear hobbing process. This paper uses three-level factorial design method to design gear hobbing experiments, and carries out mathematical and statistical analysis on the experimental results. It is found that cutting feed is the most significant machining parameter followed by hob rotation speed and depth of cut to reduce processing time and energy consumption. The prediction model of processing time and energy consumption in gear hobbing process is obtained through response surface methodology. The relative error rates of the predicted value and the actual value of the processing time and energy consumption are 0.11% and 0.09% respectively, indicating the validity of the model. Multi-objective salp swarm algorithm is used to optimize the machining parameters to minimizing processing time and energy consumption. Finally, through the comparison with the existing research results, it is concluded that the optimized machining parameters have better processing effect to achieve minimized processing time and energy consumption, which shows the effectiveness and rationality of the method proposed, and provides references for the decision-making of machining parameters in workshop.

Edge detection is a fundamental step in many machine vision or image processing applications and systems. The importance of edge detection increases as one seeks to increase the level of automation in the image processing system. The paper reports an edge detection operator which is fast in application to grey scale images and is sensitive to 'difficult' edges but not sensitive to artifacts such as scanner interlacing artifacts. The edge detection operator presented is simple but provides good detection of edges and clean and continuous edges across most of the image.

ENERGY efficient computing used to be a concern only for designers of untethered computer and mobile communication systems, where battery size and recharge intervals limited their usefulness. In the past few years, the importance of reducing energy has become a central concern for designers of tethered computers as well because of the power limitations of a standard household power outlet and because they are often deployed in large groups, in the case of server farms. To address the research issues that arise in energy efficient computing, the US Defense Advanced Projects Agency began a program several years ago under the heading Power Aware Computing and Communications (PAC/C). This has led to a wide range of new developments in energy efficient computing and communications. This special issue solicited original papers from, but not restricted to, researchers in the PAC/C program. Our goal was to show the wide range of computer related research that is concerned with minimizing energy consumption in one way or another. Our lead-off paper, “Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages,” employs genetic algorithm for module selection and scheduling under the constraints of power and area. The next paper, “Charge-Recovery Computing on Silicon,” presents an overview of energy-recovering systems, focusing on recent developments. The third paper, “A Holistic Approach to Designing Energy-Efficient Cluster Interconnects,” looks at interconnecting networks of computers and addresses the problem of designing the interconnects to be energy-efficient. The fourth paper, “Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors,” focuses on the microarchitectural level and proposes and analyzes a clustered loop buffer for VLIW-style processors. The analysis shows that such buffers are able to generate a significant amount of energy savings. The fifth paper in our series, “Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors,” moves to a higher level of abstraction and proposes a fast and efficient approach for designing and estimating energy consumption for single chip heterogeneous multiprocessors—a common platform for mobile system. The sixth paper, “An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs,” returns to the microarchitectural level. It proposes a design time instruction set minimization to reduce instruction cache power. The seventh paper, “Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations,” looks at the application level, specifically the power-performance of motion detection in an image processing application. The eighth paper, “Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes,” is a tutorial paper on sensor networks with special emphasis on their power requirements. The penultimate paper, “A Speculative Control Scheme for an Energy-Efficient Banked Register File,” again returns to the microarchitectural level and shows how low power register files can be constructed from smaller faster banks of registers. The last paper, “GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks,” proposes an adaptive scalable architecture targeted toward algorithm-specific tasks in which power is a constraint. The architectural model derives its scalability from a set of Globally Asynchronous and Locally Synchronous (GALS) building blocks.

Reliability assessment on 16 nm ultrascale+ MPSoC using fault injection and fault tree analysis

As modern image and video processing applications handle increasingly higher image resolutions, the buffering requirements between communicating functional modules increase correspondingly. The performance and cost of these applications can change dramatically depending on the implementation methods for FIFO buffers and the data delivery methods between modules. This paper introduces a new FIFO hardware mapping algorithm based on pointer-based token delivery from dataflow semantics for image and video processing applications. This approach significantly improves the performance of dataflow based implementation of image and video processing systems, and allows effective prediction of changes in performance and buffer memory requirements associated with changes in image resolution. Our pointer-based token delivery method allows indirect token delivery between actors by pointers in conjunction with use of a shared memory. Each pointer references a data block stored in the shared memory. In pointer-based token delivery, a buffer can be configured to be implemented as the combination of a small, fast FIFO and a larger, relatively cheap shared memory while providing an attractive trade-off between performance and hardware cost. We present the complete semantics of our pointer-based modeling method, systematic techniques for mapping representations using these semantics into efficient implementations, and experimental results that demonstrate the performance of the proposed pointer-based techniques.

Multiple sensing is the ability to sense the environment with the concurrent use of several sensors. There are currently a number of different sensors routinely used in image processing applications, and the trend is toward the development of more sophisticated and less expensive sensors. This trend is complemented by the development of parallel and multiprocessor architectures for processing the large amounts of data collected by these sensors. The capabilities of many image processing systems can be greatly enhanced by the organized use of several types of sensors and by the develop-ment of methods capable of integrating the collected data in a way that can yield information otherwise unavailable, or hard to obtain, from any single type of sensor. The advantage in using several similar sensors has already been demonstrated in the context of dynamic scene analysis, where information contained in a sequence of visual intensity images (including stereoscopic images) has been integrated with the twofold objective of obtaining the three-dimensional description and the motion of objects in space. The advantage in using several different sensors is clear from the quite obvious observation that different sensors are sensitive to different signals, each one of which can reveal a particular set of properties of the sensed environment. This paper discusses the advantages of multiple sensor integration/fusion with different sensors through image processing and identifies a number of associated problems. It reviews preliminary work on the solution of these problems and indicates the direction of future research.

Image segmentation is a very important aspect in the field of image processing. According to certain principles, it will be divided into a number of small regional disjoint. Small region is a sense sets of common attributes of the connectivity pixels. The so-called connectivity which refers to the fact that any two points in the pool existing a connectivity path between all belong to the set. Pulse coupled neural networks was proposed based on the brain simultaneously pulsed release phenomenon of the visual cortex of the cats, monkeys, and other animals, the similar input data can be outbreak synchronized through interrelated neurons. The digital image can be processed by pulse coupled neural networks, the pixels of space based approach and brightness can be made up to a group. Pulse coupled neural networks has a good nature in image processing applications, which can effectively for the various aspects of image processing, and it can be used in the image processing system. Experimental results show that the method can achieve better image segmentation and have a common applicability.

Fuzzy C-means (FCM) clustering method has been widely used in image segmentation that plays an important role in a variety of applications in image processing and computer vision systems, but the performance of FCM heavily relies on the initial cluster centers which are difficult to determine. To solve the problem, the paper proposes a new hybrid method for image segmentation, which first randomly generates a population of initial clustering solutions and then uses an evolutionary algorithm to search for better clustering solutions; at each iteration, the FCM method is applied on each initial clustering solution to produce its segmentation result. Among a set of popular evolutionary algorithms, we find that the biogeography-based optimization (BBO) metaheuristic exhibits good performance on the considered problem. Besides the basic BBO, we have also proposed a set of improved BBO versions in their combination with FCM for image segmentation. Computational experiments on a set of test images show that the proposed method has significant advantage over the basic FCM algorithm and those hybrid algorithms combining FCM with other evolutionary algorithms such as artificial bee colony and particle swarm optimization.

The diffusion weighted image (DWI) technique is routinely used for diagnosis and treatment of early stroke due to its superior performance, especially when compared with conventional magnetic resonance image (MRI) for detection of acute ischemic stroke. Using DWI examination, this paper proposes an application of image processing in a computer-aided diagnosis system, which can effectively calculate the volume size and provide 3D reconstruction data of a lesion. The potential benefits of using our system include the higher accuracy of acute stroke lesion definition, the reduced time and procedure of calculating the volume, and providing 3D reconstruction image of stroke patients, which can effectively assist doctors in making more accurate diagnoses and treating patients in a more convenient way. Compared with the traditional method, the experimental results have shown the superior performance of this proposed system.

In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 19-22 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.KeywordsDiscrete Cosine TransformCache SizeData CacheMemory ArchitectureEmbed ProcessorThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

In this paper we propose a methodology that takes into account bit-width to optimize area and power consumption of hardware architectures provided by high level synthesis tools. The methodology is based on a bit-width analysis using information that comes from the designer. This bit-width information is propagated through a graph which models the application. The resulting annotated graph enables datapath structure optimizations for high level synthesis without increasing dramatically its processing time (complexity: O(n)). The methodology was applied to several signal and image processing applications. Our results demonstrate the effectiveness of the approach. It can be also applied in a more general design context for sizing the data of an application knowing the input data formats and their potential correlation.

Stochastic encoding represents a value using the probability of ones in a random bit stream. Computation based on this encoding has good fault-tolerance and low hardware cost. However, one of its major issues is long processing time. We have to use a long enough bit stream to represent a value to guarantee that random fluctuations introduce only small errors to final computation results. For example, for most digital image processing algorithms, we need a 512-bit stream to represent an 8-bit pixel value stochastically to guarantee that the final computation error is less than 5%. To solve this issue, this paper proposes to share bits between adjacent bit streams to represent adjacent deterministic values. For example, in image processing applications, the bit stream which represents the current pixel value can share parts of the bits in the bit stream which represents the previous pixel value. We use an image contrast stretching algorithm to evaluate this method. Our experimental results show that the proposed methods can improve the performance by 90%.

Currently, background subtraction is being actively studied in many image processing applications. Nuclear Norm Minimization (NNM) and Weighted Nuclear Norm Minimization (WNNM) are commonly used background subtraction methods based on Robust Principal Component Analysis (RPCA). However, these techniques approximate the RPCA rank function and take the form of an iterative optimization algorithm. Therefore, due to the approximation, the NNM solution can not converge if the number of frames is small. In addition, the NNM and WNNM processing times are delayed because of their iterative optimization schemes. Thus, NNM and WNNM are not suitable for real-time background subtraction. In order to overcome these limitations, this paper presents a real-time background subtraction method using tensor decomposition in accordance with the recent tensor analysis research trend. In this study, we used the closed form TUCKER2 decomposition solution to omit the iterative process while retaining the L1 norm of the RPCA rank function. This proposed method allows for convergence even when the number of frames is small. Compared to NNM and WNNM, the proposed method reduces the processing time by more than 80 times and has a higher precision even when the number of frames are less than 10.

Image smoothing, or denoising, is a very important pre-processing operation in almost all applications of digital Image processing ranging from enhancement of space-probe pictures to automatic finger print identification. In this paper we present the results of a comparative analysis study of four different smoothing techniques for digitized binary images.The techniques considered are: Majority smoothing, Directional logic smoothing, Majority smoothing with contour checking, and a simple l-D median filter-type smoothing. The first three are two dimensional. Three criteria for judging the performance of the examined techniques are selected, which are: The qualitative effect on the image quality, the processing time, and the effect on the image compression efficiency. The four techniques are implemented and tested on a wide range of test images. A sample of the test images, original and smooth ed, will be presented to illustrate quantitatively the effect of the different methods. The l-D smoothing was found to require the least processing time , while the majority smoothing method was found to have the best effect on the compression efficiency (average increase of 20% ). The study was done using the Wang Professional Image Computer (PIC), which is a microcomputer-based imaging system.

Modern embedded systems consist of heterogeneous computing resources with diverse energy and performance trade-offs. This is because these resources exercise the application tasks differently, generating varying workloads and energy consumption. As a result, minimizing energy consumption in these systems is challenging as continuous adaptation between application task mapping (i.e. allocating tasks among the computing resources) and dynamic voltage/frequency scaling (DVFS) is required. Existing approaches have limitations due to lack of such adaptation with practical validation (Table I). This paper addresses such limitation and proposes a novel adaptive energy minimization approach for embedded heterogeneous systems. Fundamental to this approach is a runtime model, generated through regression-based learning of energy/performance trade-offs between different computing resources in the system. Using this model, an application task is suitably mapped on a computing resource during runtime, ensuring minimum energy consumption for a given application performance requirement. Such mapping is also coupled with a DVFS control to adapt to performance and workload variations. The proposed approach is designed, engineered and validated on a Zynq-ZC702 platform, consisting of CPU, DSP and FPGA cores. Using several image processing applications as case studies, it was demonstrated that our proposed approach can achieve significant energy savings (>70%), when compared to the existing approaches.