An Implementation and Optimization of Artificial Neural Network Based on Intra-chip Heterogeneous

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In recent years, deep learning has been widely used in various fields, and powerful computing power is the basis for supporting the development of deep learning. Heterogeneous computing has become a mainstream direction for improving computing power due to its excellent performance and flexible structure. However, it also requires a lot of optimization from the algorithm to the hardware structure to perform large scale operations under low power conditions. In order to solve the above problems, this paper proposes a flexible optimization and implementation based on intra-chip heterogeneous. First, we divide tasks and assign code segments of the same operation to the same subtask. Secondly, according to the requirements of subtasks, a reusable and configurable acceleration kernel is developed in the FPGA, which has high multiplexing rate and flexibility. In addition, the performance and power consumption of the core is improved by optimizing the memory access and interface communication. The experiment result on a convolutional neural network with proposed method demonstrates that it only takes 1.1ms to identify a picture and power is 2.5W. Compared with the efficiency of running on ARM, the speed of convolution operation based on heterogeneous platform is 46.8 times faster.