An Improvement on LDPC Coded Queued Codes

DOI: 10.1049/cp:20061337 ISBN: 0 86341 644 6 Location: Hangzhou, China Conference date: 6-9 Nov. 2006 Format: PDF The BER performance of presented quasi-cyclic (QC) low-density parity-check (LDPC) codes is not good as that of randomly constructed LDPC codes, while the lack of structure of randomly constructed LDPC codes implies serious disadvantages in terms of storing and accessing a large parity-check matrix. To solve the problems, this paper proposes a design of good quasi-cyclic (QC) low-density parity-check (LDPC) codes, the obtained algebraically structured codes have large minimum distances and good BER performance. The proposed design is based on index matrices, which determines the shifts of the circulant matrices of the sparse parity-check matrices. Compared with the presented design of QC LDPC codes, the designed QC LDPC codes are free from girth 4, sometimes free from girth 6, and have much larger minimum distances. Based on the algebraic code structure, the conditions of the girth and minimum distance of the codes are found. The BER performance of the designed QC LDPC block codes compares with that of randomly constructed LDPC codes for any block lengths. Better BER performance is obtained by increasing the circulant size of the base QC code. Simulations verify the construction of the QC LDPC codes to be valid. (4 pages) Inspec keywords: AWGN channels; error statistics; channel coding; algebraic codes; parity check codes; sparse matrices Subjects: Algebra; Other topics in statistics; Codes

This letter gives a random construction for Low Density Parity Check (LDPC) codes, which uses an iterative algorithm to avoid short cycles in the Tanner graph. The construction method has great flexible choice in LDPC code’s parameters including codelength, code rate, the least girth of the graph, the weight of column and row in the parity check matrix. The method can be applied to the irregular LDPC codes and strict regular LDPC codes. Systemic codes have many applications in digital communication, so this letter proposes a construction of the generator matrix of systemic LDPC codes from the parity check matrix. Simulations show that the method performs well with iterative decoding.

Big data storage demands larger cluster. The increasing size of the cluster may lead to failures of larger number of nodes. To provide reliable big data storage, replications are not cost-effective and does not provide a robust solution to prevent data loss. Traditional erasure codes applied in the RAID system such as Reed-Solomon (R-S) based solutions have limitations in providing high reliability. This is because higher reliability requires erasure codes with larger size. The computational cost of the R-S codes increase quadratically with the number of failures the R-S codes can tolerate for the same redundancy rate. It has been shown that Low Density Parity Check (LDPC) codes have lower computational cost and repair network traffic compared with R-S based solutions. Unfortunately, there does not exist a construction method for LDPC codes with larger size to control the computational cost and repair traffic. In this paper, a novel method is proposed to construct a family of LDPC codes - expanCodes with expandable sizes. The proposed expanCodes allows the encoding and decoding complexity remain unchanged with the increase of the size of the LDPC codes. As a result, increased reliability can be achieved without additional computation and repair traffic. The proposed expanCodes is integrated with the Hadoop system. Simulations show that more than 29% decrease in terms of encoding and decoding latency compared with R-S based solutions.

Turbo codes are attractive compared with Low Density Parity Check (LDPC) codes for Forward Error Correction (FEC) applications mainly due to their superior performance, especially at low Signal-to-Noise Ratio (SNR) such as are common in Powerline channels. For example, IEEE 1901-FFT PHY used the Turbo coding scheme defined in the HomePlug AV standards. However, patent fees are usually required for each turbo-code enabled manufactured device. The objective of this paper is to examine whether unlicensed LDPC codes, with optimized choices of block lengths, could be a viable alternative for future Powerline Communications (PLC) applications. The paper shows that the performance of the LDPC codes can approximate that of the Turbo codes with higher block lengths, on channels with typical and realistic PLC characteristics. The paper also shows that the additional complexity associated with this increase in block length can be mitigated by the use of Quasi-Cyclic LDPC (QC-LDPC) codes.

Low Density Parity Check (LDPC) codes have capacity-approaching performance over several channels of interest. In practice, for good block-error rate performance, the girth of the Tanner graph of an LDPC code needs to be as high as possible. In theory, to show that block-error rate approaches zero for increasing block-lengths, the girth of the Tanner graph sequence needs to tend to infinity with block-length. To meet these requirements, we construct sequences of large-girth irregular LDPC codes for a given degree-distribution pair (DDP) by applying a general node splitting algorithm on large girth graphs. The obtained Tanner graph meets the required DDP up to a suitable approximation. By optimizing the node-splitting method and using suitable large-girth graphs, we show code constructions with smaller block length for the same girth, when compared to previous constructions. Similar gains in block length are observed in the construction of sequences of large-girth protograph LDPC codes. Simulations, over a binary erasure channel, confirm the gains in block-error rate obtained by the large girth construction.

We propose a novel concatenated coding scheme combined Low Density Parity Check(LDPC) code and vertical Bell Labs layered space-time (VBLAST) code to improve the bit error rate (BER) performance for Free-space optical (FSO) communication links with On Off Keying(OOK) modulation. In the scheme, π-rotation encoding and belief-propagation (BP) decoding algorithm are employed in LDPC code, and minimum mean-square error (MMSE) soft-decision decoding algorithm is used for VBLAST code. Moreover, a joint iterative detection and decoding algorithm of VBLAST code and LDPC code is used to improve the overall link performance. At last, the BER of the proposed scheme over lognormal atmospheric turbulent fading channels is analyzed by using Monte Carlo method. The result shows that the BER of the proposed concatenated coding scheme is much improved than that only use VBLAST code scheme.

In this paper, a random Low-Density Parity-Check (LDPC) code is proposed for Noncontiguous Orthogonal Frequency Division Multiplexing (NC-OFDM) Cognitive Radio (CR) systems. Unlike other encoding schemes which achieve a system code rate of only 1/4 when half of the subcarriers are active, the proposed scheme achieves a system code rate of 1/2. The LDPC code is used to enhance the data transmission rate. A new channel model comprised of a binary erasure channel concatenated with an uncorrelated fading channel and an AWGN channel is adopted for NC-OFDM CR systems. Moreover, the adopted channel model is employed with density evolution algorithm to obtain good degree distribution pairs for the LDPC code. Thereafter, a modified shortest-path algorithm is used to construct the parity-check matrix for the LDPC code. Simulation results show that the proposed LDPC code performs well in terms of both error rate and data transmission rate.

The application of Low Density Parity Check (LDPC) code in the anti-interference systems has drawn an increasing attention, due to its admiring performance which is very close to the theory limit. This paper focuses on a LDPC encoded slow frequency hopping (SFH) communication system with partial-band interference. Firstly, a modified soft- decision algorithm based on the utilization of interference information is proposed, and its performance is compared with some other soft-decision methods. Secondly, with numerical simulation, the influence of code rate, code length and the number of symbols per hops on the performance of the system with partial band noise interference is illustrated and examined in detail. Considering the great influence of hops per symbol on the performance, interleaver should be used and its influence on the performance is further examined by simulation. Finally, some constructive advises for the design of LDPC coded SFH system are given. Simulation results show that, with a reasonable design, the SFH system with LDPC code could achieve a desirable performance.

Low Density Parity Check (LDPC) codes have been widely used in communications systems due to their high error correction capabilities. Recently these codes are also investigated for being exploited in high performance storage systems, especially when Non-Volatile Memory (NVM) technologies are used. The main drawback of using LDPC codes in storage systems with a high number of parallel channels is the increased hardware complexity and cost, especially when variable rate codes are used. In this work, we present an architecture of a NVM-based storage system that dynamically adapts the LDPC's rate to the aging conditions of the storage device in order to maximize its lifetime capacity while keeping low its hardware complexity. In order to decrease the system's complexity we propose a PCIe-based architecture that uses a pool of LDPC decoders shared by all NVM channels and we study its effect on the system's lifetime capacity and the achievable I/O data rate.

In this paper, we propose a concatenated code by combining a Recursive Systematic Convolutional (RSC) code with a Low-Density Parity-Check (LDPC) code. The proposed concatenated code is encoded in parallel by an RSC encoder and an LDPC encoder without interleavers between them. When decoding the proposed concatenated code, the information bits are decoded by two decoding algorithms, and soft information is exchanged between the RSC decoder and the LDPC decoder. This allows for the elimination of wrong codewords output by each decoder. The use of an LDPC code allows us to halt the decoding process when the valid codeword is obtained. We evaluate the error rate performance of the proposed concatenated code by computer simulations. We show that the proposed concatenated code does not have a high error floor, and achieves better BLock Error Rate (BLER) performance than either conventional LDPC codes or conventional turbo codes in the high Eb/No region. We also show that since the proposed concatenated code can correct wrong codewords output by each decoder, it achieves better BLER than the regular LDPC code at the same Bit Error Rate (BER).

Summary form only given. The ultimate performance limit or threshold of low-density parity-check (LDPC) codes is close to capacity over various memoryless channels (S.-Y. Chung, IEEE Trans. Info. Theory, vol. 47, pp. 657-670, 2001). Since the capacity of binary-input partial response (PR) channels is unknown, we estimate the capacity by calculating the threshold of capacity-approaching LDPC codes over these channels. We assume a BCJR equalizer for the channel and a sum-product message-passing decoder for the LDPC code. We also assume that the log-likelihood ratios (LLRs) in the channel BCJR and the LDPC decoder are Gaussian. We use our results to guide the design of decoder schedules that minimize the number of computationally expensive BCJR steps. The threshold calculation method can be used to optimize the left and right degree sequences of the LDPC code factor graph, using fast linear programming methods, to provide better thresholds than regular codes.

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.

In communication systems, the transmitted data is corrupted by channel perturbations, such as noise and fading, which affect the reliability of the received data. Error correction codes are employed to mitigate channel perturbations. However, design and implementation of good and efficient error correction codes remains an open problem. In this paper, Low Density Parity Check (LDPC) codes are considered as they provide a reasonable trade-off between computational complexity and reliability. Good LDPC codes should ideally provide low complexity, close to capacity acheivable transmission rate, high coding threshold, and high decoding stability. In this paper, we investigate a joint LDPC code optimization algorithm using Genetic Algorithm (GA) and Linear Programming (LP) to determine the variable nodes and check nodes degrees distributions. EXIT chart analysis and Frame Error Rate (FER) performance are used to validate the proposed method.

<div> <h2>Abstract</h2> <p><strong>Objective:</strong> In the code theory, parallel concatenation of codes becomes more popular after the introduction of turbo codes. In recent years, the Low Density Parity Check (LDPC) code has found remarkable advancement and has seen them outshine turbo codes in terms of performance especially in the error floor and higher code rate. The main objective of this paper is to address the various techniques of a parallel concatenation of LDPC code in code theory. <strong>Method/Finding:</strong> To reduce the complexity of encoding and decoding for longer codes various parallel concatenation of LDPC coding methods were introduced and the performance was compared with other work. <strong>Novelty:</strong> When a longer block length is used, the parallel LDPC decoder is suffered from the complexity of prohibitive implementation. To overcome this issue and to achieve the best performance for longer codes, the different methods for parallel concatenation of LDPC codes were introduced with reduced complexity. This will helps to break the long and complex LDPC code into less complex and smaller LDPC to distribute the decoding and encoding load. Also, this will provides scalability and scope for improving the performance of LDPC codes in practical delay-sensitive and energy-aware applications.</p> <p><strong>Keywords:</strong> Parallel concatenation; LowDensity ParityCheck (LDPC); turbo codes; Parallel Concatenated Gallager Codes (PCGC)</p> </div> <div></div> <div> </div>

본 논문에서는 OFDM 시스템에서 고속 처리와 성능 향상을 위한 LDPC 코드 기반 결정 궤환 등화기(Decision Feedback Equalizer: DFE)를 제안한다. LDPC 코드는 우수한 오류 정정 능력과 Shannon의 채널 용량에 근접하는 성능을 갖는다. 그러나, 많은 parity 검사 행렬과 반복 횟수를 가진다는 단점이 있다. 제안된 시스템에서는 판정된 신호와 복호기 사이의 신호의 MSE(Mean Square Error)를 등화기로 피드백한다. 이러한 방법을 사용하면 추정된 채널 응답을 보정해 주기 때문에 성능을 향상시킬 수 있다. 또한, 동일한 성능에서 피드백이 포함되지 않은 시스템보다 낮은 반복 횟수를 갖기 때문에 시스템의 복잡도를 줄일 수 있다. 시뮬레이션을 통해 다중 경로 채널에서 CFO(Carrier Frequency Offset)와 위상 잡음이 고려된 OFDM 시스템의 성능을 평가하여 제안 시스템의 우수성을 보인다. In this paper, we propose a decision feedback equalizer based on LDPC(Low Density Parity Check) code for the fast processing and performance improvement in OFDM system. LDPC code has good error correcting capability and its performance approaches the Shannon capacity limit. However, it has longer parity check matrix and needs more iteration numbers. In our proposed system, MSE(Mean Square Error) of signal between decision device and decoder is fed back to equalizer. This proposed system can improve BER performance because it corrects estimated channel response more accurately. In addition, the proposed system can reduce complexity because it has a lower number of iterations than system without feedback at the same performance. Simulation results evaluate and show the performance of OFDM system with the CFO and phase noise in multipath channel.