An in-depth study on WENO-based techniques to improve parameter extraction procedures in MOSFET transistors

This paper gives and explains the simulation results of single-event burnout (SEB) hardening in a power metal-oxide semiconductor field-effect transistor U-Shape Metal Oxide Semiconductor Field Effect Transistor (trench-gate MOSFET). It includes p+ plug enlargement and adds a buffer layer that is between the epitaxial layer and substrate. These two hardening solutions are compared and the optimized structure that can prevent SEB is given. The single event gate-rupture (SEGR) threshold voltages in different linear energy transfers are also compared with SEB results. In addition, the simulation results show that the change of gate bias can influence the occurrence of SEGR, and the natural radiation environment at cryogenic temperatures is also considered.

A novel Si/sub 1-x/Ge/sub x/ channel Metal Oxide Semiconductor field effect transistor (MOSFET) is described. Si/sub 1-x/Ge/sub x/ alloy used was grown by means of molecular beam epitaxy (MBE). The band structure of the Si/sub 1-x/Ge/sub x/ channel MOSFET is different from that of the silicon channel MOSFET. Because of this, the performance of the former is better than that of the latter. In the present study, 3-inch-diam, N-type, oriented silicon wafers with resistivity of 2 ohm-cm were used. First, Si/sub 1-x/Ge/sub x/ (x=0.1-0.7) layers were grown, with a thickness 0.5-0.8 nm. Then, a silicon buffer layer was grown. After that, a gate oxide layer 15 nm thick was grown at a temperature of 800/spl deg/C. Following polysilicon growth, polysilicon was doped by implantation of phosphorus. The formations of source and drain were by also by implantation. The I-V curves of output with different dopant concentration were obtained. The main direct current parameters of measured Si/sub 1-x/Ge/sub x//Si MOSFET are: the threshold voltage V/sub T/=-1.3 V, the transconductance G/sub m/=100-130 siemens, the breakdown voltage of source and drain is 13-16 V.

Previous research on flyback power factor correction (PFC) converters exposes some inherent shortcomings, such as high‐voltage spike on the metal oxide semiconductor field effect transistor (MOSFET), frequency variation, pulsating input current and hard switching operation. This study presents a new topology for PFC applications named zero‐voltage switching (ZVS) current‐fed flyback converter to not only achieve spike‐free voltage, ZVS on the MOSFETs, but also improve the input current quality. By utilising quasi‐z‐source configuration, the voltage spikes on the MOSFET are effectively eliminated using only a capacitive clamper, resulting in no‐loss consumption. Low‐voltage MOSFETs with low on‐resistance Rds(on) are used to improve the efficiency. In addition, by taking advantage of the average current mode control with the continuous conduction mode operation, the input current perfectly tracks the input voltage. To demonstrate the circuit's feasibility, a 100–140 V input, 28 V/5 A output laboratory prototype was built. The experimental results showed that the proposed topology completely eliminated the voltage spikes on the MOSFETs. The efficiency was improved using low Rds(on) MOSFETs, and ZVS was achieved. In summary, the proposed topology meets the high efficiency and high‐input current quality requirements.

This note investigates temperature effects on dosimetry using a metal oxide semiconductor field effect transistor (MOSFET) for radiotherapy x-ray treatment. This was performed by analysing the dose response and threshold voltage outputs for MOSFET dosimeters as a function of ambient temperature. Results have shown that the clinical semiconductor dosimetry system (CSDS) MOSFET provides stable dose measurements with temperatures varying from 15 °C up to 40 °C. Thus standard irradiations performed at room temperature can be directly compared to in vivo dose assessments performed at near body temperature without a temperature correction function. The MOSFET dosimeter threshold voltage varies with temperature and this level is dependent on the dose history of the MOSFET dosimeter. However, the variation can be accounted for in the measurement method. For accurate dosimetry, the detector should be placed for approximately 60 s on a patient to allow thermal equilibrium before measurements are taken with the final reading performed whilst still attached to the patient or conversely left for approximately 120 s after removal from the patient if initial readout was measured at room temperature to allow temperature equilibrium to be established.

The authors report a sensing scheme to detect the translocation of small particles through a fluidic channel. The device connects the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a fluidic circuit and monitors the FET’s drain current to detect particles. They demonstrate that amplification can be achieved from both the fluidic circuit and the MOSFET. The results show that a 0.7% volume ratio of the particle to the sensing microchannel can lead to 28%–56% modulation of the MOSFET’s drain current. The minimum volume ratio detected is 0.006%, which is about ten times smaller than the lowest detectable volume ratio reported in the literature.

In this study we propose the fabrication of advanced high-speed complementary metal oxide semiconductor field effect transistor (AHCMOS) by combining a P-carbon nanotube with n-metal oxide semiconductor (NMOS) on a single chip. The target is to achieve extremely high speed low-power dissipating miniaturized device with improved functionalities.  The technology of conventional metal oxide semiconductor field effect transistor (MOSFET) and nanotechnology are applied in this research. A P-carbon nanotube is complemented with the conventional NMOS all embedded on the same chip.  Although it is possible to fabricate both a P and N carbon nanotube to form a complementary pair, and also a PMOS and NMOS to form a complementary pair, however in this research we propose a hybrid structure with carbon nanotube transistor technology and complementary MOSFET technology. This device therefore combines the best characteristics of carbon nanotube technology and CMOS technology to provide enhanced logic functions that are optimized for the high-speed, low-power systems and miniaturized size ideal for very large scale integration (VLSI).

The effects of longitudinal and latitudinal polysilicon grain boundaries on the performance metal oxide semiconductor field effect transistors (MOSFETs) fabricated on large-grain polysilicon-on-insulator (LPSOI) have been investigated. Unlike conventional thin-film-transistors (TFTs) with random grain distribution, MOSFETs fabricated on the LPSOI film contains the combination of only longitudinal or latitudinal grain boundaries. Longitudinal GBs parallel to the direction of current flow has smaller impact to the current flow, but provided extra leakage current that caused early device shortage, especially in wide devices. The latitudinal GBs perpendicular to the direction of current flow offered higher resistance to the inversion carriers thus causing lower current drive, higher threshold voltage, and gentler subthreshold slope. The result of the study can be used to optimize device design for high performance on MOSFETs on the LPSOI substrate.

This work presents the potential benefits of Dual Material Gate and Lateral Asymmetric Channel on high-k gate stack double gate (GS-DG) metal oxide semiconductor field effect transistor (MOSFET). This study is a comparison between single material (SM), dual material (DM), and dual material single halo (DM-SH) for GS-DG MOSFETs. The key idea behind this investigation is to provide a physical explanation for the improved performance exhibited by different device design guidelines. The DM devices are found to be significantly better performance as compare to their SM counterparts as they show higher drive current with same threshold voltage. We can say theses devices are more immune to Short Channel Effects (SCEs) at nanoscale regime.

Any applications would prefer to have the circuits which are of high speed and consumes less power. To meet these requirements, the scaling of the circuits which are generally designed using Metal Oxide Semiconductor Field Effect Transistors (MOSFET) is done. Too much scaling down of the transistors or the integrated circuits (IC) affects the channel of the transistors causing Short Channel Effects (SCEs) which in turn affecting the reliability and performance of the circuits. To avoid this issue, a substitute of MOSFET known as Fin Field Effect Transistors (FinFE T) is used in the circuits. This helps to reduce the scaling needed and also has the better performance than the MOSFETs. This work demonstrates the advantageous performance of the FinFE Ts by implementing some of the basic building blocks of the digital circuits such as Inverter, NAND gate, NOR gate, a combinational circuit like Full Adder and a sequential circuit like SR Flip Flop. The designs are simulated using HSPICE tool at 45 nm technology. The parameters such as static power dissipation, dynamic power dissipation, rise time and fall time are examined through waveforms. The circuits with MOSFETs have the higher values from the parameters than the circuits with FinFETs.

Analysis of effects of MOSFET parasitic capacitance on non-synchronous buck converter electromagnetic emission

The effects of electron–electron scattering on the electron energy distribution, as well as substrate and gate currents in short channel MOSFETs (metal-oxide-semiconductor field-effect transistors) are explored using the convective scheme, or CS, a method of characteristics. Effects of electron–electron scattering are explored for a MOSFET with uniform doping in the channel as well as for an asymmetric device structure, a focused-ion-beam (FIBMOS) transistor, for both 70 nm and 250 nm channel length devices. Effects of electron–electron scattering on a standard 35 nm channel length MOSFET are also included. The high substrate doping that is required for such short channel length devices leads to large electric fields. The purpose of the FIB implant is to improve hot-carrier reliability by reducing the electric field in the channel. Electron–electron scattering increases the amount of electrons in the tail, despite the fact that the applied potential is significantly below the threshold for injection of electrons into the gate oxide. The ratio of gate-to-substrate current, Ig/Isub, is investigated as an indicator of the level of degradation. At such short channel lengths, there are degrading and non-degrading components of gate and substrate current. The non-degrading components of gate and substrate current correlate strongly, so that the ratio of Ig/Isub is an efficient indicator of device degradation. The energy thresholds for impact ionization and for emission of electrons into the gate oxide are crucial in determining the ratio of these currents. The substrate and gate currents obtained indicate that hot-carrier effects continue to be an issue for device performance, even for nanometer-scale devices. The density of electrons is higher at very short channel lengths due to the need to have shallow junctions and leads to a greater amount of Coulomb collisions. Increased Coulomb collisions may lead to strongly reduced lifetimes in nanometer-scale devices.

An ultrafine trench isolation, by which a narrow channel metal oxide semiconductor field effect transistor (MOSFET) can be isolated with excellent electrical properties, was formed using a new fabrication process. A void‐free shape was realized by two‐step filling, and the trench edge shapes were drastically improved by oxide spacer formation. Down to the ultranarrow field space of 0.13 μm, the isolation breakdown voltage and the parasitic MOSFETs threshold voltage were maintained as high as 7.7 V and more than 6 V. The reduction in the effective channel width for the MOSFET, furthermore, was estimated to be as small as 0.05 μm, while it was shown that kink‐free MOSFET subthreshold characteristics were kept even without a sidewall implantation to suppress the concentration of the electric field at the channel edges.

Modeling and simulation of electronic structure, material interface and random doping in nano-electronic devices

By using a split-gate-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with four finger gates, the small-area inversion layer conductance in the regime of ballistic transport has been investigated. This device enables us to perform four-probe measurements in a very small area, by which the large series resistances of two-dimensional inversion layers are deduced. At 4.2 K, clear conductance plateaus that reflect the valley degeneracy of Si-MOSFETs on a (100) wafer were observed without correction. Furthermore, under the threshold voltage, clear Coulomb blockade oscillations were also observed. The interplay between ballistic transport and Coulomb blockade would be an interesting subject for further study.

The threshold voltage instability of silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs) has drawn extensive attention. However, there is limited research on the recovery performance of the threshold voltage of SiC MOSFETs. In this paper, the performance and the physical mechanism of the threshold voltage recovery have been studied with experiments and simulations. It is found that no more than 0.25 V short-term recovery of the threshold voltage can be observed within one hour after the gate bias. Furthermore, the threshold voltage drift can undergo a more complete long-term recovery even exceeding 75% of the dynamic threshold voltage drift with higher recovery temperature and more negative gate bias. The findings are intended for better understanding and management of potential threshold voltage drift in device tests and applications.