An Indigenous Flight Control System Test

For the shortcomings high prices and big volume of traditional university laboratory experiment platform for automatic control principle, the paper designs the simple experiment system for automatic control principle based on double SCM system of AT89S52 and ATmega16 and virtual experimental software platform of LabVIEW. The system includes hardware and monitoring software interface of two parts. The system hardware part adopts the modular design concept, mainly including power module, signal generator module, basic experimental link module, control system link module and the data acquisition module. One signal generator and the data acquisition module contain lower level computer software programming. The upper level computer software is written by LabVIEW, and consists of serial parameters adjustment, display of data received, playback of data stored, and other functions. After the completion of the entire system design, the experimental result is consistent entirely with the simulation waveform of MATLAB through the step response for typical second-order oscillation link, and proves that the design of experiment system is feasible.

Closed-loop HIRF experiments were performed on a fault tolerant flight control computer (FCC) at the NASA Langley Research Center. The FCC used in the experiments was a quad-redundant flight control computer executing B737 Autoland control laws. The FCC was placed in one of the mode-stirred reverberation chambers in the HIRF Laboratory and interfaced to a computer simulation of the B737 flight dynamics, engines, sensors, actuators, and atmosphere in the Closed-Loop Systems Laboratory. Disturbances to the aircraft associated with wind gusts and turbulence were simulated during tests. Electrical isolation between the FCC under test and the simulation computer was achieved via a fiber optic interface for the analog and discrete signals. Closed-loop operation of the FCC enabled flight dynamics and atmospheric disturbances affecting the aircraft to be represented during tests. Upset was induced in the FCC as a result of exposure to HIRF, and the effect of upset on the simulated flight of the aircraft was observed and recorded. This paper presents a description of these closed-loop HIRF experiments, upset data obtained from the FCC during these experiments, and closed-loop effects on the simulated flight of the aircraft.

Hardware-In-The-Loop (HIL) simulation has an important role on rapid prototyping and developing control software for various application areas. Having deterministic time response and high computational power, a personal computer (PC) with a real-time operating system is an efficient platform solution for HIL simulation needs. Fast development time and cost efficiency of simulation platform are other important issues for reduction of total production lead time and overall cost. In this paper; taking into consideration all these aforementioned aspects, we propose a HIL simulation software framework for PC target. Building a MATLAB/Simulink diagram and using available device drivers, an ordinary user can develop and execute HIL simulation of his/her controller. The proposed framework is developed for PC platforms that have Linux Xenomai real-time operating system infrastructure. The framework contains a Simulink Xenomai target control module, a Graphical User Interface (GUI) and a Simulink device driver library. Also, to illustrate the performance and feasibility of the proposed framework, a Xenomai real-time driver model (RTDM) based driver for Quanser Q8 data acquisition board has been implemented. Experiments performed on servo control of a two degree of freedom (DOF) robot illustrated that proposed framework meets hard real-time requirements

The wide use of GUI (Graphic User Interface - graphical User Interface) is one of the great achievements in today's computer development. μC/GUI, as one of the mature GUI technology, becomes more and more common in embedded products. It has a small kernel, occupying less resources, high performance and high reliability etc, and can be designed as powerful and complex man-machine interface for embedded system. it uses the STM32 development board as the carrier. Software system is composed of hardware drivers, μC/OS-Ⅱ real-time operating system, FATFS file system, μC/GUI graphical interface system and so on. Analyzing the process and steps of μC/GUI transplantation, through the design of interface we can realizes simple human-computer interaction function. After tested, it works well.

In 1996, ARINC 653 Part 1 (653p1) was published, which defines a standard Real-Time Operating System (RTOS) API called the APplication EXecutive (APEX). APEX defines mandatory RTOS services including the notions of time and space partitioning, and is targeted at large, complex Integrated Modular Avionics (IMA) systems. In 2012, ARINC 653 Part 4 (653p4) was developed, which defines a subset of 653p1 capabilities intended to address systems that do not require the size, complexity, or features of IMA systems. As such, 653p4 brings the benefit of 653p1-style standards compliance to more devices on aircraft, such as the majority of the Line Replaceable Units (LRUs) on next-generation aircraft. In this paper, we discuss ARINC 653p4 in contrast with 653p1.

The Hardware-In-the-Loop (HIL) simulation system for on-orbit docking dynamics is a large-scale complex test equipment. It establishes working conditions for the docking mechanism similar with those on orbit. The kernel of above dynamics HIL simulation system is a mechanical force and movement actions simulator. Besides the mechanical force and movement actions simulator, it also includes an environmental simulator, a microgravity simulator and so on. In a narrow mind, the HIL simulation system for on-orbit docking dynamics refers to the mechanical force and movement action simulator. It is a feedback system which consists of the dynamics simulation model and real-time simulaton computer, the hardwares under test, the force and torque sensor, the motion simulator. The research topic of this paper is limited in above narrow mind. The HIL simulation system for on-orbit docking dynamics is a key technology that played important roles in the lunar excursion of America and in the assembling and re-supplying of Russian MIR space station. Morden space programme enhance the requirements to the HIL simulation for spacecraft docking dynamics. International Space Station (ISS) program also required that the ISS Common Berthing Mechanism (CBM) testing on ground simulator should be performed under operational vacuum and thermal conditions (Office of NRBMP, 1999). In the early days, the physical simulators played main roles in docking dyniamics tests. Because of the development of computor and the complexity of modern docking mechanism, the HIL simulation technology is applied in the docking dynamics simulation. The dynamic docking test system (DDTS) is setup in US (Gates & Graves, 1974), and the integated testing system for docking mechanism was built in former Soviet (Peng et al., 1992). In1980s, docking dynamic test facility (DDTF) was created for testing the handleslatch docking mechanism (Crimbert & Marchal, 1987). National space development agency of Japan built the rendezvous and docking operation test system (RDOTS) testing threepoints handles-latch docking mechanism (Lange & Martin, 2002). The HIL simulation for spacecraft on-orbit docking is a attractive and promising research field. Lim et al. (1989) modeled and simulated the Stewart platform of DDTS. They pointed

For SOC devices, it is sometimes required to route high frequency analog signals (>10MHz) to the device under test (DUT). It is common to use an analog signal generator within the test system to provide these signals. However, production test systems for such devices often contain many more digital pins than analog signal generators. Therefore, it is advantageous to utilize the digital pins whenever possible in order to leave the analog resources available for other needs. This work reports how a digital channel (pin) of an SOC test system can be used, leaving the analog signal source available for other purposes. This solution may be used to provide something as simple as a clock pulse or a filtered CW tone. One common need for a high frequency analog signal is when supplying the DUT with an analog reference clock signal for the phase-locked looped functionality within the DUT. This low-level sinusoidal-like signal must be extremely stable with low phase noise. One of the most critical items of concern in these applications is the phase noise of the signal.

The evolution of software testing technologies has significantly reduced software testing execution times, but the test design and generation are still often implemented with slow manual-oriented methods. Model-based testing (MBT) offers automation to test design and generation, and different MBT solutions are familiar from research, but more effort needs to be done to adopt MBT for industrial use. Hardware in the loop (HIL) is a simulation and testing technique used in the development and testing of embedded systems. HIL is a challenging application field for MBT due to complex and non-deterministic nature of some embedded systems. To tackle this problem, the authors present a novel prototype platform in which online and offline MBT is applied to HIL environment. MBT in general has been introduced for HIL in scientific literature before, but the application of online MBT in HIL is a novel approach. The whole novel MBT in HIL prototype platform along with the used MBT tool, platform architecture and MBT process are presented accompanied by experimental results and analysis of two case studies with an example embedded system under test.

A wide range of Radio Frequency (RF) assemblies require testing during their development and production. These include amplifiers, mixers, filters, up converters, down converters, antennas, phase shifters, power dividers, power combiners, Integrated Master Assemblies (IMAs), Weapons Replaceable Assemblies (WRAs), Line Replaceable Units (LRUs) and radio subassemblies. Though there are many differences between the RF assemblies, they all require a test system that is accurate, reliable and traceable while simultaneously minimizing test times. Other important attributes of a test platform for RF assemblies are that it must be calibrated, fully-characterized and incorporate self-test functionality. The test platform must also include a digital control solution for triggering, communicating with Units Under Test (UUT) and interfacing with handlers, fixtures, etc. Finally, the software for the test equipment must also be considered. Typical software functionality would include sequencing, reporting, testing, calibration, and self-test. While it is certainly possible to develop a test system specific to each type of RF assembly; there are many benefits to developing a common RF test platform that includes the functionality listed above.

Data acquisition and Signal Processing is an important part of frequency modulated continuous wave (FMCW) radar system. In recent year P2ET-LIPI was developing FMCW navigation radar system in portable size. The main component of data acquisition for navigation radar is highspeed Analog to Digital Conversion (ADC) USB-2020 board and signal processing algorithm has been developed using Visual C# 2015 Community Edition. USB-2020 board has two channel ADC on board with 12 bits resolution and operated in a burst-io mode to get maximum sampling rate at 20 MS/s. A timing generator for synchronization between ADC and linear frequency modulation (LFM) chirp generator is developed using Complex Programmable Logic Device (CPLD) Max II series based on VHSIC hardware description language (VHDL). Signal processing unit consists of windowing function to reduce side- lobe suppression, Fast Fourier Transform (FFT) function to get range information and adaptive threshold using three algorithms of Constant False Alarm Rate (CFAR): Cell Averaging (CA), Order Statistic (OS) and Variable Index (VI) CFAR. The experiment shows that the data acquisition module can capture In-phase and Quadrature (I/Q) beat signal and signal processing algorithm can detect object/target from the noise.

A dual-redundant flight control computer system is proposed to ensure the stability and reliability of flight. A multiplexing structure suitable for a dual-redundant flight control computer system is presented. And, minimized flight control computer was designed considering the size of the system. It is difficult to determine which one is a faulty system, unlike with triple-redundancy systems, because it has only two signal inputs. We propose using the model predictive voting algorithm to isolate the fault system in a dual-redundancy system. This algorithm consists of a built-in test, signal slope test, and analytic redundancy test. The simulation was performed by receiving the Pulse-Width Modulation obtained by the controller as an input in the same way as the real-time conditions. And, simulation is performed to analyze the performance of the voting algorithmKeywordsDual-redundant systemFlight control computerModel-predictive voting algorithm

With the increasing communication frequencies in 6G networks, high-speed terahertz (THz) modulation signal generation has become a critical research area. This study first proposes an on-chip high-speed THz modulation signal generation system based on lithium niobate (LN), which integrates a pair of racetrack resonator-integrated Mach–Zehnder modulators (RMZMs) with a chirped periodically poled lithium niobate (CPPLN) waveguide. The on-chip system combines near-infrared electro-optic modulation and cascaded difference-frequency generation (CDFG) for high-speed THz modulation signal generation. At 300 K, utilizing two input optical waves at frequencies of 193.55 THz and 193.14 THz, this on-chip system enables high-speed THz modulation signal generation at 0.41 THz, with a 1 Gbit/s modulation rate and a 0.25 V modulation voltage. During the simulation, when the intensity of the input optical waves is 1000 MW/cm2, the generated 0.41 THz signal reaches a peak intensity of 21.24 MW/cm2. Furthermore, based on theoretical analysis and subsequent simulation, the on-chip system is shown to support a maximum modulation signal generation rate of 7.75 Gbit/s. These results demonstrate the potential of the proposed on-chip system as a compact and efficient solution for high-speed THz modulation signal generation.

According to the demand for multi-channel and reliable high-speed data transmission of the test for environment of the rockets' launch .the article designed and developed a 64-channel data acquisition module based on MLVDS. With FPGA as the core, using VHDL to write logic control program to control data acquisition and reading process, add the CRC check arithmetic to improve the reliability, through MLVDS interface upload data to master communication module and the upper machine .The test results show that the data acquisition module is good, bit error rate is low and the transmission rate of up to reached 35 MB/S, satisfies the requirement of system design, and has been applied in rocket environment test system.

In complex systems, testing each interface of a system separately is not a coherent way of testing and it reduces test quality. Especially in design verification tests, increasing test quality can be achieved by testing system level reactions and responses of all interfaces together simultaneously considering the system as a whole. In this study, a test system created for design verification tests of four different units through Hardware-in-theloop (HIL) simulation is to be explained. Design verification tests covering whole interfaces of Unit Under Test (UUT) are demonstrated with also simulations of units to be connected to UUT. The overall test system is divided into two main parts as automatic test equipment (ATE) design and HIL simulation design. The design process of ATE includes test requirements, specifications and identifications of all interfaces which belong to interconnected units in the system. The hardware selections and connections between them are accomplished for four different UUTs in such a manner that they can be tested together or separately. In the design process of HIL simulation, each sub-system connected to UUTs and UUTs themselves are considered separately. The requirements for each sub-system and each UUT are met within the interface control documents. In order to increase the quality of test, communications and the control of the electrical interfaces between each sub-system are implemented in real time. The communication interfaces consist of RS422, RS485, MILSTD-1553, Telnet and CANopen. The reactions and responses of each UUT are collected and HIL simulation is improved. Finally, the discussions about the approach of design verification tests of four different UUTs within HIL simulation and the improvement of the test quality are revealed. Further in this study, the test approach used by DEICO for HIL is discussed in detail.

In order to meet the tomato color sorting system with the requirements of multi-channel data acquisition and real-time processing, [ ]firstly, a multi-channel color digital acquisition and processing technique program based on FPGA were proposed . Then, a multi-channel data acquisition and real-time parallel processing system was built. The RGB color sensors were slected as detection components and the FPGA chip EP1C3T144C8 was slected as a core of data acquisition and processing. Meanwhile, ports of signal acquisition and the solenoid valve control were adopted a two-way analog switch HC4051 for saving I/O ports of FPGA. Thirdly, under the modular design and module reuse principles, we developed all modules with VHDL Language in QuartusII development environment. Finally, RTL and time sequence simulation for the system were done. The results showed that the connections between the modules accord with control logics. [²»´o¶O accorded ¹ýE¥E½] The performance of system time sequencev are good, which can meet with the requirements of real-time processing of tomato color sorting. On these bases, we also conducted a tomato sorting test verification. The results showed that the average accuracy of sorting is 98.70% and coefficient of variation is 0.01. This results can meet requirements of production.