An Integer Arithmetic-Based Sparse Linear Solver Using a GMRES Method and Iterative Refinement

When dealing with graphics operations that must be fast (like the inner loops of rendering algorithms), I usually like to do calculations with fixed-point arithmetic (that is, scaled integers) rather than floating point arithmetic. The exact scaling factor used can have some interesting effects on the speed and errors in the calculation. In this article, I'll give some titbits I've discovered or picked up from others about this. In particular, I'll talk about some of the advantages of using odd numbers of the form 2/sup n/-1 as scaling factors. The motivation for this discussion is the desire to do arithmetic on pixel values: red, green, blue, or alpha. These values are in the range 0...1, so all numbers you see here are positive. In the discussion that follows, I'll use floating point as a testbed and as scaffolding to derive integer formulas. All final calculations take place using only integer arithmetic. >

Chapter 7 - Arithmetic Operations

The purpose of this paper is to summarize proposed specifications for floating-point arithmetic and elementary functions. The topics considered are: the base of the number system, precision control, number representation, arithmetic operations, mother basic operations, elementary functions, and exception handling. The possibility of doing without fixed-point arithmetic is also discussed. The specifications are intended to be entirely at the level of a programming language such as Fortran. The emphasis is on convenience and simplicity from the user's point of view. The specifications are not complete every detail, but it is intended that they be complete in spirit — some further details, especially syntatic details, would have to be provided, but the proposals are otherwise relatively complete.

Diffraction calculations in few-bit formats, such as single-precision floating-point and fixed-point numbers, are important because they yield faster calculations and lower memory usage. However, these methods suffer from low accuracy owing to the loss of trailing digits. Fresnel diffraction is widely known to prevent the loss of trailing digits. However, it can only be used when the paraxial approximation is valid. In this study, a few-bit diffraction calculation method that achieves high accuracy without using any approximation is proposed. The proposed method is derived only by rationalizing the numerator of conventional formulas. Even for scenarios requiring double-precision floating-point numbers using conventional methods, the proposed method exhibits higher accuracy and faster computation time using single-precision floating-point numbers.

In this paper, we present an efficient way of implementing OpenGL ES 1.1 3D graphics API library for the environments with hardware-supported OpenGL facility, typically as desktop PCs. Although OpenGL ES was started from the existing OpenGL features, it rapidly became the standard 3D graphics library customized for embedded systems through introducing fixed-point arithmetic operations, buffer management with fixed-point data type supports, completely new texture mapping functions and others. Currently, it is the official 3D graphics API for Google Android, Apple iPhone, Sony PlayStation3, etc. In this paper, we achieved improvements on the arithmetic operations for the fixed-point number representation, which is the most characteristic data type for OpenGL ES 1.1. For the conversion of fixed-point data types to the floating-point number representations for the underlying OpenGL, we show the way of efficient conversion processes even with satisfying OpenGL ES standard requirements. We also introduced a specialized memory management scheme to manage the converted data from the buffer containing fixed-point numbers. In the case of texture processing, the requirements in both standards are quite different, and thus we used completely new software-implementations. Our final implementation of OpenGL ES library provides all of more than 200 functions in the standard specification and passed its conformance test, to show its compliance with the standard. From the efficiency point of view, we measured its execution times for several OpenGL ES-specific application programs and achieved remarkable improvements.

본 논문에서는 데스크탑과 같이 OpenGL 기능이 전용 하드웨어로 제공되는 환경을 대상으로, OpenGL ES 1.1 표준을 효율적으로 구현하는 방법을 제시한다. OpenGL ES는 기존의 OpenGL 표준을 바탕으로 하였지만, 고정소수점 연산, 이를 수용하는 버퍼 기능, 완전히 새로운 텍스처 처리 등의 도입으로, 임베디드 시스템에 특화된 3차원 그래픽스 라이브러리로 새롭게 제정되어, 구글 안드로이드, 애플 아이폰, 플레이스테이션3 등에서 공식 3차원 그래픽스 API로 채택되었다. 본 논문에서는 OpenGL ES의 특징적 자료형인 고정소수점 표현에 대한 산술 연산들을 개선하였고, 특히 고정소수점 자료형들을 부동소수점 형태로 변환하여 하위의 OpenGL API로 넘기는 과정에서 표준을 준수하면서도 효율적인 처리가 가능하도록 하였다. 새로 도입된 고정소수점 자료형을 허용하는 버퍼 기능에 대해서는 변환된 자료들을 별도의 메모리 공간에서 관리하는 방식으로 속도 향상에 중점을 두었으며, 요구 사항이 완전히 달라진 텍스처 처리 부분은 전체 기능을 별도의 소프트웨어로 완전히 새롭게 구현하였다. 최종 구현 결과인 OpenGL ES 라이브러리는 OpenGL ES 1.1 표준에 규정된 총 200여 함수를 제공하며, 표준인증 테스트를 완전히 통과하여 1.1 표준을 완벽히 만족시켰음을 보였다. 수행 속도 면에서는 OpenGL ES에 특화된 응용 프로그램들에 대한 처리 속도 측정에서 기존의 구현 사례들에 비해 최대 33.147배의 속도 향상을 가져왔으며, 동일한 범주의 구현 사례들 중에서 가장 빠른 구현 결과이다. In this paper, we present an efficient way of implementing OpenGL ES 1.1 standard for the environments with hardware-supported OpenGL API, such as desktop PCs. Although OpenGL ES was started from the existing OpenGL features, it becomes a new three-dimensional graphics library customized for embedded systems through introducing fixed-point arithmetic operations, buffer management with fixed-point data type supports, completely new texture mapping functionalities and others. Currently, it is the official three dimensional graphics library for Google Android, Apple iPhone, PlayStation3, etc. In this paper, we achieved improvements on the arithmetic operations for the fixed-point number representation, which is the most characteristic data type for OpenGL ES. For the conversion of fixed-point data types to the floating-point number representations for the underlying OpenGL, we show the way of efficient conversion processes even with satisfying OpenGL ES standard requirements. We also introduced a simple memory management scheme to mange the converted data for the buffer containing fixed-point numbers. In the case of texture processing, the requirements in both standards are quite different and thus we used completely new software-implementations. Our final implementation result of OpenGL ES library provides all of over than 200 functions in OpenGL ES 1.1 standard and completely passed its conformance test, to show its compliance with the standard. From the efficiency viewpoint, we measured its execution times for several OpenGL ES-specific application programs and achieved at most 33.147 times improvements, to become the fastest one among the OpenGL ES implementations in the same category.

In digital communication applications, floating-point arithmetic is generally used to conduct performance evaluation studies of new proposed algorithms. This is typically limited to theoretical performance evaluation in terms of communication quality and error rates. For a practical implementation perspective, using fixed-point arithmetic instead of floating-point reduces significantly the costs in terms of area occupation and energy consumption. However, this implies a complex conversion process, particularly if the considered algorithm includes complex arithmetic operations with high accuracy requirements and if the target system presents many configuration parameters. In this context, the purpose of the paper is to investigate the influence on error rate performance related to the implementation of minimum mean-squared error (MMSE) linear turbo-equalization algorithm for multiple-input multiple-output (MIMO) systems utilizing fixed-point rather than floating-point arithmetic.

Vector normalization is an important process in several algorithms. It is used in classical physical calculations, mathematical techniques, and machine learning, which has witnessed significant advancements in recent years. Normalization and regularization ensure the stability of solutions and play an important role in algorithm convergence. Normalization typically refers to the division of elements by their norm. Division should not be used in algorithmic implementations because its computational cost is considerably higher than that of multiply–add operations. Based on this, there is a well-known method referred to as the fast inverse square root (FISR) algorithm in floating-point calculations (IEEE754). In deeper-level embedded systems that require fast responses or power efficiency, integer instead of real number arithmetic (floating-point number arithmetic) should be used to increase speed. Conversely, in deeper-level embedded systems that require fast responses or power efficiency, integer arithmetic should be used instead of real number arithmetic (floating-point number arithmetic) to increase speed. Therefore, embedded engineers encounter problems in instances in which they use integer arithmetic for implementation, but real number arithmetic is required to compute vectors and other higher-dimensional algebra. There is no conventional normalization algorithm similar to the FISR algorithm for integer arithmetic; however, the proposed pseudo-normalization achieves vector normalization within a restricted domain using only multiply–add operations and bit shifts. This allows for fast and robust operations, even for low-performance MCUs that do not have power-efficient FPUs. As an example, this study demonstrates the computation of the arctangent (Arctan2 function; atan2(y, x)) with high precision using only integer multiply–add operations. In this study, we proposed a method of vector normalization using only integer arithmetic for embedded systems and confirmed its effectiveness by simulation using Verilog. The research results can contribute to various fields such as signal processing of IMU sensor data, faster artificial intelligence training, and efficient rendering of computer graphics.

Floating-point arithmetic is ever-present in computer systems. All most all computer languages has supports a floating-point number types. Most of the computer compilers called upon floating-point algorithms from time to time for execution of the floating-point arithmetic operations and every operating system must be react virtually for floating-point exceptions like underflow and overflow. The double-precision floating arithmetic is mainly used in the digital signal processing (filters, FFTs) applications, numerical applications and scientic applications. The double-precision floating arithmetic operations are the addition, the subtraction, the multiplication, and the division. Among the all arithmetic operations, multiplication is widely used and most complex arithmetic operation. The double-precision (64-bit) floating point number is divide into three fields, Sign field, Exponent field and Mantissa field. The most significant bit of the number is a sign field and it is a 1-bit length, next 11-bits represents the exponent field of the number and remaining 52-bits are represents the mantissa field of the number. The double-precision floating-point multiplier requires a large 52×52 mantissa multiplications. The performance of the double-precision floating number multiplication mainly depends on the area and speed. The proposed work presents a novel approach to decrease this huge multiplication of mantissa. The Urdhva Tiryagbhyam technique permits to using a smaller number of multiplication hardware compared to the conventional method. In traditional method adding of the partial products are separately done and it takes more time in comparison with the proposed method. In proposed method the partial products are concurrently added with the multiplication operaton and it can reduce the time delay. The double-precision floating multiplier is implemented using Verilog HDL with Xilinx ISE tools on Virtex-5 FPGA.

Transversal adaptive filters for digital signal processing have traditionally been implemented into DSP processors due to their ability to perform fast floating-point arithmetic. However, with its growing die size as well as incorporating the embedded DSP block, the FPGA devices have become a serious contender in the signal processing market. Although it is not yet feasible to use floating-point arithmetic in modern FPGAs, it is sufficient to use fixed-point arithmetic and still achieve tap-weight convergence for adaptive filters. This paper examines the feasibility of implementing an adaptive algorithm, namely the LMS algorithm, based on fixed-point arithmetic, using the Altera Stratix device.

We study the accuracy of a classical approach to computing complex square-roots in floating-point arithmetic. Our analyses are done in binary floating-point arithmetic in precision p, and we assume that the (real) arithmetic operations +, —, x, ÷, √ are rounded to nearest, so the unit roundoff is u = 2−p. We show that in the absence of underflow and overflow, the componentwise and normwise relative errors of this approach are at most 7/2u and √37/2u, respectively, and this without having to neglect terms of higher order in u. We then provide some input examples showing that these bounds are reasonably sharp for the three basic binary interchange formats (binary32, binary64, and binary128) of the IEEE 754 standard for floating-point arithmetic.

A matrix-based procedure is presented for computing the output roundoff power for filters implemented with floating-point arithmetic. The filter's computational structure is represented in terms of a product of matrices, known as a factored state variable description. The quantities needed to compute the output roundoff noise power are obtained from the factored state variable description by matrix manipulation. The expression for output roundoff noise power is shown to be of the same form as that for fixed-point arithmetic roundoff noise. Comparison indicates that, under very general conditions, fixed-point arithmetic provides better roundoff noise performance than floating-point arithmetic. Several examples are provided.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

There is increasing interest about floating-point arithmetics in field programmable gate arrays (FPGAs) because of the increase in their size and performance. FPGAs are generally good at bit manipulations and fixed-point arithmetics, but they have a harder time coping with floating-point arithmetics. An architecture used to construct high-performance floating-point components in a Virtex-4 FPGA is described in detail. Floating-point adder/subtracter and multiplier units have been constructed. The adder/subtracter can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12).

Geometric algorithms are usually described assuming that arithmetic operations are performed exactly on real numbers. A program implemented using a naive substitution of floating-point arithmetic for real arithmetic can fail, since geometric primitives depend upon sign-evaluation and may not be reliable if evaluated approximately. Geometric primitives are reliable if evaluated exactly with integer arithmetic, but this degrades performance since software extended-precision arithmetic is required.

The paper describes a sequential MD algorithm in which distances between particles are evaluated using fixed point arithmetics. Errors introduced by the method are estimated. Some simulation timings as well as fluctuations of the total energy are compared to the results obtained using floating point arithmetics.