An integer programming-based search technique for error-prone structures of LDPC codes

Low Density Parity Check (LDPC) codes have capacity-approaching performance over several channels of interest. In practice, for good block-error rate performance, the girth of the Tanner graph of an LDPC code needs to be as high as possible. In theory, to show that block-error rate approaches zero for increasing block-lengths, the girth of the Tanner graph sequence needs to tend to infinity with block-length. To meet these requirements, we construct sequences of large-girth irregular LDPC codes for a given degree-distribution pair (DDP) by applying a general node splitting algorithm on large girth graphs. The obtained Tanner graph meets the required DDP up to a suitable approximation. By optimizing the node-splitting method and using suitable large-girth graphs, we show code constructions with smaller block length for the same girth, when compared to previous constructions. Similar gains in block length are observed in the construction of sequences of large-girth protograph LDPC codes. Simulations, over a binary erasure channel, confirm the gains in block-error rate obtained by the large girth construction.

The design of moderate-length erasure correcting low-density parity-check (LDPC) codes over correlated erasure channels is considered. Although the asymptotic LDPC code design remains the same as for a memoryless erasure channel, robustness to the channel correlation shall be guaranteed for the finite length LDPC code. This further requirement is of great importance in several wireless communication scenarios where packet erasure correcting codes represent a simple countermeasure for correlated fade events (e.g., in mobile wireless broadcasting services) and where the channel coherence time is often comparable with the code length. In this paper, the maximum tolerable erasure burst length (MTBL) is adopted as a simple metric for measuring the code robustness to the channel correlation. Correspondingly, a further step in the code construction is suggested, consisting of improving the LDPC code MTBL. Numerical results conducted over a Gilbert erasure channel, under both iterative and maximum likelihood decoding, highlight both the importance of the MTBL improvement in the finite-length code construction and the possibility to tightly approach the performance of maximum distance separable codes.

The performance of iterative decoding of low density parity check (LDPC) codes over binary erasure channels can be completely characterized by the study of stopping sets. Therefore, the burst erasure correction capability of a given LDPC code can be readily quantified by searching for stopping sets within consecutive bit nodes. In this work we study the optimal permutation of the bit nodes that will result in the maximum possible burst erasure correction capability for a given LDPC code. Noting that this is essentially a combinatorial optimization problem that is highly likely to be NP-hard, we adopt a simulated annealing based approach for finding the optimal permutation. We present bounds based on stopping sets that limit the burst erasure correction capability. As part of our results, we provide interleavers that greatly improve the burst erasure correction capability of protograph quasi-cyclic LDPC codes used in the WiMax standard.

For certain degree-distribution pairs with non-zero fraction of degree-two bit nodes, the bit-error threshold of the standard ensemble of Low Density Parity Check (LDPC) codes is known to be close to capacity. However, the degree-two bit nodes preclude the possibility of a block-error threshold. Interestingly, LDPC codes constructed using protographs allow the possibility of having both degree-two bit nodes and a block-error threshold. In this paper, we analyze density evolution for protograph LDPC codes over the binary erasure channel and show that their bit-error probability decreases double exponentially with the number of iterations when the erasure probability is below the bit-error threshold and long chain of degree-two variable nodes are avoided in the protograph. We present deterministic constructions of such protograph LDPC codes with girth logarithmic in blocklength, resulting in an exponential fall in bit-error probability below the threshold. We provide optimized protographs, whose block-error thresholds are better than that of the standard ensemble with minimum bit-node degree three. These protograph LDPC codes are theoretically of great interest, and have applications, for instance, in coding with strong secrecy over wiretap channels.

Turbo codes are attractive compared with Low Density Parity Check (LDPC) codes for Forward Error Correction (FEC) applications mainly due to their superior performance, especially at low Signal-to-Noise Ratio (SNR) such as are common in Powerline channels. For example, IEEE 1901-FFT PHY used the Turbo coding scheme defined in the HomePlug AV standards. However, patent fees are usually required for each turbo-code enabled manufactured device. The objective of this paper is to examine whether unlicensed LDPC codes, with optimized choices of block lengths, could be a viable alternative for future Powerline Communications (PLC) applications. The paper shows that the performance of the LDPC codes can approximate that of the Turbo codes with higher block lengths, on channels with typical and realistic PLC characteristics. The paper also shows that the additional complexity associated with this increase in block length can be mitigated by the use of Quasi-Cyclic LDPC (QC-LDPC) codes.

Big data storage demands larger cluster. The increasing size of the cluster may lead to failures of larger number of nodes. To provide reliable big data storage, replications are not cost-effective and does not provide a robust solution to prevent data loss. Traditional erasure codes applied in the RAID system such as Reed-Solomon (R-S) based solutions have limitations in providing high reliability. This is because higher reliability requires erasure codes with larger size. The computational cost of the R-S codes increase quadratically with the number of failures the R-S codes can tolerate for the same redundancy rate. It has been shown that Low Density Parity Check (LDPC) codes have lower computational cost and repair network traffic compared with R-S based solutions. Unfortunately, there does not exist a construction method for LDPC codes with larger size to control the computational cost and repair traffic. In this paper, a novel method is proposed to construct a family of LDPC codes - expanCodes with expandable sizes. The proposed expanCodes allows the encoding and decoding complexity remain unchanged with the increase of the size of the LDPC codes. As a result, increased reliability can be achieved without additional computation and repair traffic. The proposed expanCodes is integrated with the Hadoop system. Simulations show that more than 29% decrease in terms of encoding and decoding latency compared with R-S based solutions.

Effect of channel mismatch on decoding performance of low density parity check (LDPC) codes over binary symmetric channel (BSC) under sum-product algorithm (SPA) is analyzed in this paper. Density evolution is employed in theoretical analysis to get optimal initial value for SPA. Based on the results, a modified SPA algorithm is proposed. When decoding using this modified SPA algorithm, no channel information is needed at the decoder side. This will be of significant value for time-varying channels. Theoretical claims from density evolution are confirmed by extensive simulations. Our simulations show that by fixing the initial value for all channel conditions, decoding performance can be improved. One channel state estimation algorithm is proposed in this paper based on the error detection ability of LDPC codes. Maximum number of iterations taken when decoding a LDPC code can be dynamically adjusted according to the estimated channel state. Further performance improvements can be achieved by using the dynamic iteration number adjusting scheme together with the modified sum-product algorithm.

We propose a novel concatenated coding scheme combined Low Density Parity Check(LDPC) code and vertical Bell Labs layered space-time (VBLAST) code to improve the bit error rate (BER) performance for Free-space optical (FSO) communication links with On Off Keying(OOK) modulation. In the scheme, π-rotation encoding and belief-propagation (BP) decoding algorithm are employed in LDPC code, and minimum mean-square error (MMSE) soft-decision decoding algorithm is used for VBLAST code. Moreover, a joint iterative detection and decoding algorithm of VBLAST code and LDPC code is used to improve the overall link performance. At last, the BER of the proposed scheme over lognormal atmospheric turbulent fading channels is analyzed by using Monte Carlo method. The result shows that the BER of the proposed concatenated coding scheme is much improved than that only use VBLAST code scheme.

In this paper, a random Low-Density Parity-Check (LDPC) code is proposed for Noncontiguous Orthogonal Frequency Division Multiplexing (NC-OFDM) Cognitive Radio (CR) systems. Unlike other encoding schemes which achieve a system code rate of only 1/4 when half of the subcarriers are active, the proposed scheme achieves a system code rate of 1/2. The LDPC code is used to enhance the data transmission rate. A new channel model comprised of a binary erasure channel concatenated with an uncorrelated fading channel and an AWGN channel is adopted for NC-OFDM CR systems. Moreover, the adopted channel model is employed with density evolution algorithm to obtain good degree distribution pairs for the LDPC code. Thereafter, a modified shortest-path algorithm is used to construct the parity-check matrix for the LDPC code. Simulation results show that the proposed LDPC code performs well in terms of both error rate and data transmission rate.

A family of rate-compatible capacity-approaching codes is obtained by spatially coupling multiple identical copies of rate-compatible base codes. The base code consists of a given regular low-density parity-check (LDPC) code and a parameter-adjustable repeat-accumulate (RA) extension. The RA-extension repeatedly accumulates all of the variable nodes of the given LDPC code by q + 1 times to generate q + 1 blocks of accumulated nodes, in which all of the accumulated variable nodes in the first q blocks and the α-fractional accumulated variable nodes in the last block are transmitted. The spatially coupled versions of the base codes, called RA-extended spatially coupled LDPC (SC-LDPC) codes, achieve arbitrary rates by simply adjusting parameters q and α, and thus they are rate-compatible. The potential thresholds of the base code ensembles are calculated to predict the iterative decoding performance of the proposed RA-extended SC-LDPC codes. Numerical results and simulations show that the authors’ proposed rate-compatible codes are capacity-approaching over binary erasure channels.

Low density parity-check (LDPC) codes are a class of linear block codes that are decoded by running belief propagation (BP) algorithm or log-likelihood ratio belief propagation (LLR-BP) over the factor graph of the code. One of the disadvantages of LDPC codes is the onset of an error floor at high values of signal to noise ratio caused by trapping sets. In this paper, we propose a two stage decoder to deal with different types of trapping sets. Oscillating trapping sets are taken care by the first stage of the decoder and the elementary trapping sets are handled by the second stage of the decoder. Simulation results on the regular PEG (504,252,3,6) code and the irregular PEG (1024,518,15,8) code shows that the proposed two stage decoder performs significantly better than the standard decoder.

The multiple description coding framework is well-suited for the transmission of images in the presence of transmission errors. However, it has been mainly explored for idealized channels, where packets are either received correctly or not at all. In more realistic scenarios, bitstreams are affected by bit-level noise and error correcting codes must be employed. In the proposed scheme, the input image is decomposed into wavelet coefficients that are encoded using lattice vector quantization for the generation of multiple descriptions. Low-density parity-check (LDPC) codes are used for the protection of each stream, while joint decoding exploits the correlation between the multiple descriptions. The proposed joint source-channel decoding scheme can provide robust transmission of images by introducing a controlled amount of redundancy that can be used for error recovery. Results are presented for image transmission over binary symmetric and Gaussian channels.

The application of Low Density Parity Check (LDPC) code in the anti-interference systems has drawn an increasing attention, due to its admiring performance which is very close to the theory limit. This paper focuses on a LDPC encoded slow frequency hopping (SFH) communication system with partial-band interference. Firstly, a modified soft- decision algorithm based on the utilization of interference information is proposed, and its performance is compared with some other soft-decision methods. Secondly, with numerical simulation, the influence of code rate, code length and the number of symbols per hops on the performance of the system with partial band noise interference is illustrated and examined in detail. Considering the great influence of hops per symbol on the performance, interleaver should be used and its influence on the performance is further examined by simulation. Finally, some constructive advises for the design of LDPC coded SFH system are given. Simulation results show that, with a reasonable design, the SFH system with LDPC code could achieve a desirable performance.

Low Density Parity Check (LDPC) codes have been widely used in communications systems due to their high error correction capabilities. Recently these codes are also investigated for being exploited in high performance storage systems, especially when Non-Volatile Memory (NVM) technologies are used. The main drawback of using LDPC codes in storage systems with a high number of parallel channels is the increased hardware complexity and cost, especially when variable rate codes are used. In this work, we present an architecture of a NVM-based storage system that dynamically adapts the LDPC's rate to the aging conditions of the storage device in order to maximize its lifetime capacity while keeping low its hardware complexity. In order to decrease the system's complexity we propose a PCIe-based architecture that uses a pool of LDPC decoders shared by all NVM channels and we study its effect on the system's lifetime capacity and the achievable I/O data rate.

In communication systems, the transmitted data is corrupted by channel perturbations, such as noise and fading, which affect the reliability of the received data. Error correction codes are employed to mitigate channel perturbations. However, design and implementation of good and efficient error correction codes remains an open problem. In this paper, Low Density Parity Check (LDPC) codes are considered as they provide a reasonable trade-off between computational complexity and reliability. Good LDPC codes should ideally provide low complexity, close to capacity acheivable transmission rate, high coding threshold, and high decoding stability. In this paper, we investigate a joint LDPC code optimization algorithm using Genetic Algorithm (GA) and Linear Programming (LP) to determine the variable nodes and check nodes degrees distributions. EXIT chart analysis and Frame Error Rate (FER) performance are used to validate the proposed method.