An integrated neurocomputing system

The paper presents a graphical blockdiagram based programming tool, which is a new software development system for digital signal processing (DSP). This system provides a blockdiagram editor; therefore, the DSP system can be easily built by connecting functional blocks as described in the signal-flow graph. A block library is set up, which includes basic signal processing functions and some frequently used high level signal processing functions like FIR, IIR, FFT, etc. A friendly graphic user interface (GUI) based on the ‘X-Window’ system is developed to support each design step. Users can then improve their design easily according to the GUI's response. To guarantee the correctness of the circuits designed, the debugging and verifying capabilities are embedded in our system. The full system is combined with a structural silicon compiler, which we developed previously. Several designs will be illustrated as examples. It has been shown that this tool will be suitable for DSP system design by using a silicon compiler

This project aimed to develop an effective and efficient GridRPC-based environment for multiple clusters of computers distributed on the Grid. It contains programming and execution environments for GridRPC applications. The programming environment allows users to deploy GridRPC services and develop GridRPC applications to consume the existing services. In order to make the Grid transparent to the users, the GridRPC execution environment is equipped with many mechanisms for resource discovery, resource selection, request scheduling and dispatching. Especially, composite services and request bundling mechanisms are introduced and examined together with the aids of multithreaded programming techniques. They are useful to improve performance for embarrassingly parallel applications.

Chapter 5 - A Specialized Silicon Compiler and Programmable Chip for Language Recognition

In the context of heterogeneous networks, like clusters of workstations, the design of programming and execution environments aims both to easily express parallelism and distribution of applications, at conception level, and to adapt automatically their execution to fluctuations that may appear in the evolution of applications or in resources availabilities. We present the ADAJ environment (adaptive distributed applications in Java), targeted towards Java applications, which addresses these aims, through conceptual tools offered by the programming environment and through a dynamic load balancing mechanism, integrated at the middleware level. At a conception level, the developer has the possibility of easily activating processing in a MIMD programming model, using library calls. At the execution level, the efficiency of execution in ADAJ exploits an observation mechanism, which allows to acquire information on processing behaviour in order to dynamically redistribute load, by object migrations.

The SIL-ICON compiler is a software system for the specification, interpretation, prototyping, and generation of icon-oriented systems. The system design of the SIL-ICON compiler is presented. The icon system G, the icon dictionary ID, the operator dictionary OD, and the extended task action grammar ETAG are described. An application example to design a text editor using the Heidelberg icon set is also presented in detail. >

The authors report on an experiment whose main purpose was to identify the difficulties of integrating formal verification with conventional VLSI CAD (computer-aided design) methodology. The investigation was conducted using the Tamarack microprocessor designed for concrete experimentation. The authors decided to construct an implementation of Tamarack using GENESIL, a silicon compiler, in order to investigate the issues involved in the transition between a formal specification and the notation required as input to this VLSI CAD tool. The main conclusion is that the most effective use of formal hardware verification will be at the higher levels of VLSI system design, with lower levels best handled by conventional VLSI CAD tools. >

In complex modern day electronic systems, far more time is spent in designing the boards, writing the software to drive and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Unfortunately, most of the research in computer-aided design has been focussed on the more glamorous ASIC design problem, as a result of which the design methodologies and tools at the system level are much more primitive than at the chip level. We have developed a design framework for application-specific systems, called SIERA, that addresses the higher level aspects of system design, including multichip design issues at the board-level, and hardware-software codesign and integration, in addition to the design of individual ASICs. SIERA allows rapid-prototyping of multiboard systems where the functionality is implemented using a mix of dedicated hardware modules and ASICs, as well as software running on programmable hardware modules. A key step in the design methodology provided by SIERA is that of generating the physical implementation of the system hardware from a description of the system architecture. The analogue of this problem at the chip level is referred to as silicon assembly or silicon compilation. In this paper we address this problem at the system level, and describe how the generation and interfacing of board-level modules, board-level physical design, simulation of custom boards, and the overall management of board design are handled in SIERA. While some of the problems could be solved by adapting or extending techniques from the existing ASIC design tools, others required new approaches. Case-studies of several real-life applications are also presented to demonstrate the effectiveness of the board-level physical design methodology embodied in SIERA compared to the traditional PCB design systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This book presents a synthesis of recent works concerning reactive system design. The term `reactive system' has been introduced in order to avoid ambiguities often involved with the term `real-time system' which, while being best-known and suggestive, has been assigned so many different meanings that it is almost inevitably misunderstood. Industrial Process control system, transportation control and supervision systems, signal processing systems, etc. are examples of the systems we have in mind. Four programming languages are presented, which share the same underlying synchronous model: based on Robin Milner's pioneering works about synchronous process algebras, this model consists in considering that a program instantaneously reacts to events, or that the machine execution time is negligible with respect to the response delays of its environment. Using this abstract point of view, the time behavior of a system can be formalized in a very simple and elegant way. The languages presented are ESTEREL, a textual imperative language; ARGOS, a graphical language inspired by STATECHARTS; and LUSTRE and SIGNAL, two declarative languages. After a tutorial description of the languages, illustrated by various examples, a set of related tools is presented: compilers to sequential and distributed code, silicon compilers, verification tools.

The intelligent revenue operations platform integrates artificial intelligence, natural language processing, and machine learning to transform fragmented business processes into cohesive, automated workflows. This platform addresses critical challenges in lead management, quote-to-cash processes, and compliance requirements by implementing autonomous company research, intelligent classification algorithms, and adaptive workflow automation. Upon identifying a new lead, the system performs comprehensive research across multiple sources, conducts sophisticated profile analysis, determines appropriate industry classifications, and evaluates transaction behaviors—all without manual intervention. The architecture extends through the entire revenue lifecycle, automating quoting, contract generation, order processing, and revenue recognition while maintaining regulatory compliance. Implementation experiences across SaaS and manufacturing industries demonstrate significant efficiency improvements, enhanced decision-making capabilities, and measurable financial benefits. The system's modular design and integration methodology enable adaptation to diverse organizational contexts while addressing data quality, system integration, and change management challenges

This paper discusses an integrated, workstation-based software system in order to adapt the trend to digital and integrated design of small satellite and nano-satellite and formation flying small satellite or nano-satellite satellites. The system integrates Satellite Tools Kit(STK) with great demonstration and verification and satellite orbit design software faced to customer by STK/CON function. From the point of view of satellite customer, considered payload restriction, coverage restriction, TT&C communication restriction and space vehicle launching site restriction, satellite orbit design software is developed. After combined satellite orbit design software and STK, an integrated system for satellite orbit design and mission analysis is built. It is provided with design, demonstration, verification and great data report and access of satellite orbit, according to different missions of respective satellite customer. The system is used to analyze, optimize and verify the project of satellite orbit design during the phase of conceptual design and study. I. Introduction HESE years, small satellites and micro/nano-satellites (formation flying satellites) have developed rapidly. In an effort to reduce the time and costs of satellite missions’ analysis, it will be necessary to put forward an integrated, workstation-based software system. As a suite of analysis software tools that addresses all phases of a satellite system’s life cycle, including policy development and design phases, Satellite Tools Kit (STK) have great analysis and verification function of communication link, coverage and real-time visualization. However, STK is lack in verification of satellite system parameter initial design from the point of satellite customer, especially corresponding orbit design of different satellite customer [1]. A novel analysis system of satellite orbital motions using the technique of virtual reality has been developed [2]. But its hardware configuration is over-complex and one or tow analysts can not perform it. That may lead to the increasing of design cost in the course of small satellites and micro/nano-satellites whole system design. The Integrated System for Satellite Orbit Design and Mission Analysis (ISSODMA) is an integrated collection of software packages for performing satellite orbit Computer Aided Design based on STK. The system combines STK with satellite orbit design software faced to customer by STK/CON function, in other words, by secondary exploitation on the basis of STK, this system can cut down the demonstration costs and design time of satellite system project, provided with designing, analyzing, certifying and optimizing the project of satellite orbit design during the proposal research stage. Thus, a single team, consisting of one or two analysts, using a single PC, can perform the satellite design support using this integrated system. This document describes the ISSODMA and its capabilities. First, Section 2 gives an overview of the system, including a summary of what the ISSODMA does and how it works. Details of the capability of integrated system are also described in Section 2. Second, as an important module of Satellite Whole System Simulation framework, the system output port also is devised in detail in Section 3, in order to support the function of data transfer during the course of satellite whole system and sub-system design and real-time simulation and selection initial parameters. Last, for the sake of evaluation the reliability and validity of the ISSODMA, an example is shown in Section 4.

The problems of security computing are becoming increasingly relevant in connection with the integration of systems into a unified global Internet. Elbrus secure computing technology allows protecting the system from the internal program errors as well as external threats. The article describes the hardware and software components of a secure execution environment for critical applications in embedded systems based on computing means of the Elbrus family. The authors describe the basis of the Elbrus secure computing concept - the idea of a descriptor and external tags. They consider the revision of the main parts of the C language library and the kernel of the Linux operating system necessary for the implementation of this environment. The study investigates the issue of passing parameters to system calls from applications running in a secure environment. For such applications, the authors consider the process of dynamic binding of the modules loaded into memory. The method for detecting cases of the use of hung links due to the use of descriptors and external tags is presented in relation to the mechanism of orders and the release of dynamic memory. The authors suggest the container virtualization technology to detect memory leaks in a safe execution environment.

To protect Android app from malicious reproduction or tampering, code obfuscation techniques are introduced to increase the difficulty of reverse engineering and program understanding. Current obfuscation schemes focus more on the protection of the meta information over the executable code which contains valuable or patented algorithms. Therefore, a more sophisticated obfuscator is needed to improve the protection on the executable code. In this paper we propose SMOG, a comprehensive executable code obfuscation system to protect Android app. SMOG is composed of two parts, an obfuscation engine and an execution environment. The obfuscation engine is at software vendor's side to conduct the obfuscation on the app's executable code, and then release the obfuscated app to the end-user along with an execution token. The execution environment is setup by integrating the received execution token, which endows the Android Dalvik VM the capability to execute the obfuscated app. SMOG is an easily deployed system which proves fine-grained level protection. The obfuscated app generated by SMOG could resist static and dynamic reverse engineering. Moreover, the benchmark result shows SMOG only costs about 5% more performance in dispatching the incoming bytecode to the proper interpreter.

In order to realize performance test and experimental research for the accessories of aircraft fuel system, a type of integrative testing system is designed in this paper. It can accomplish function and performance tests for accessories of aircraft fuel system, and also can execute fault detection experiments. The simulation model of the system is established by using the software of AMESim, and the simulation of a certain testing about ground refueling is done to test and verify the system is right or not. Simulation results show that the working process of the testing system is normal, the design of system is scientific, and the parameter setting is logical.

Scholarships are grants in the form of financial assistance given to individuals, students or students for the continuation of education. In accordance with the program guidelines issued by the Directorate General of Higher Education, it must follow the 3T principles, namely Right Target, Right Amount and Timely. Jambi Muhamamdiyah University is one of the private universities that received a quota for the scholarship, because of the large number of scholarship recipients, the university must be selective in determining who is eligible to get the scholarship. One of the methods of information technology that can support decision-making in an organization or company is the Simple Additive Weighting (SAW) method so that it can facilitate the process of managing, sorting, comparing and selecting scholarship recipients, so as to increase the efficiency and effectiveness of the work of the actors. business. The purpose of this research is to analyze and design a prototype of the Scholarship Acceptance Decision Support System with the SAW (Simple Additive Weighting) Method at the University of Muhammadiyah Jambi so as to increase the effectiveness and efficiency in receiving scholarships and to assist in providing alternative decisions in the selection of scholarship recipients. This design was made using the visual paradigm and using object-based modeling techniques to describe the analysis and design of the system, namely in the form of use case diagrams, class diagrams, and activity diagrams. This research resulted in a prototype design of the analysis system and the design of a Scholarship Acceptance Decision Support System using the SAW (Simple Additive Weighting) method at the University of Muhammadiyah Jambi. On this basis, an integrated system is needed, it is hoped that the system can be implemented directly to increase the effectiveness and efficiency of the implementation of scholarship acceptance at the University of Muhammadiyah Jambi

Conventional M-out-of-N yield models can only roughly represent many practical chip architectures. On the other hand, representative models have the drawback of computational complexity. A yield model is introduced that overcomes the limits of existing models and provides ease of computation and predictability in approximation levels. The model is versatile enough to be included in CAM/CAD programming environments. Some application examples are given to illustrate the model accuracy, ease of use, and flexibility. >