An intrusion detection algorithm for wireless networks based on ASDL

Internet of things intrusion detection model and algorithm based on cloud computing and multi-feature extraction extreme learning machine

Many temporal and modal logic languages can be regarded as subsets of first order logic, i.e. the semantics of a temporal logic formula is given as a first order condition on points of the underlying models (Kripke structures). Often the set of possible models is restricted to models which are trees. A temporal logic language is (first order) expressively complete, if for every first order condition for a node of a tree there exists an equivalent temporal formula which expresses the same condition. In this paper expressive completeness of the temporal logic language with the set of operators U (until), S (since), and X k (k-next) is proved, and the result is extended to various other tree-like structures.

This paper shows the relation between linear temporal logic and theory of languages of concurrent processes. To this purpose, we give an algebraic correspondence between temporal logic systems and some non deterministic sequential machines. This correspondence lies on an effective method which composes machines as temporal operators. So we can synthetise processes from temporal logic formulas and solve logic problems by algorithms applied to machines.KeywordsTemporal LogicLinear Temporal LogicTemporal Logic FormulaNous AllonsBranch Time Temporal LogicThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This paper considers the problem of power systems load voltage control in order to satisfy formula expresses in temporal logics. Temporal logic can be used for expressing the coordination and sequencing of multiple agent controllers. In order to implement temporal logic control of power system, the paper first construct discrete abstraction of load voltage control system through its continuous state space decomposition, and then defines some specification propositions for OLTC regulation, load shedding relay and capacitor bank switching, and finally generates the temporal logic formula for power system load voltage control. This temporal logic formula is a supervisor of multiple agent coordination control. Some cases taking temporal logic formulas as specifications were simulated, and the results display that the temporal logic control for power system control synthesis is extremely significant

Journal Article A Digest and Pattern Matching-Based Intrusion Detection Engine Get access Zhongqiang Chen, Zhongqiang Chen * 1Yahoo! Inc., Santa Clara, CA 95054, USA *Corresponding author: zqchen@yahoo-inc.com Search for other works by this author on: Oxford Academic Google Scholar Yuan Zhang, Yuan Zhang 2Department of Mathematics, Florida State University, Tallahassee, FL 32306, USA Search for other works by this author on: Oxford Academic Google Scholar Zhongrong Chen, Zhongrong Chen 3ProMetrics Inc., King of Prussia, PA 19406, USA Search for other works by this author on: Oxford Academic Google Scholar Alex Delis Alex Delis 4Department of Informatics and Telecommunications, University of Athens, Athens, 15784, Greece Search for other works by this author on: Oxford Academic Google Scholar The Computer Journal, Volume 52, Issue 6, August 2009, Pages 699–723, https://doi.org/10.1093/comjnl/bxp026 Published: 15 April 2009 Article history Received: 05 October 2008 Revision received: 14 March 2009 Published: 15 April 2009

In bounded model checking (BMC) a system is modeled with a finite automaton and various desired properties with temporal logic formulae. Property verification is achieved by translation into boolean logic and the application of SAT-solvers. bounded satisfiability checking (BSC) adopts a similar approach, but both the system and the properties are modeled with temporal logic formulae, without an underlying operational model. Hence, BSC supports a higher-level, descriptive approach to system specification and analysis. We compare the performance of BMC and BSC over a set of case studies, using the Zot tool to translate automata and temporal logic formulae into boolean logic. We also propose a method to check whether an operational model is a correct implementation (refinement) of a temporal logic model, and assess its effectiveness on the same set of case studies. Our experimental results show the feasibility of BSC and refinement checking, with modest performance loss w.r.t. BMC.

In this paper, a motion planning system based on predictive control and temporal logic specifications is established for the welding dual-arm robot with gantry. Firstly, based on the spatial structure of the dual-arm robot with gantry, a novel mathematical model is presented between the joint variables and the terminal attitude and the quaternion replaces the Euler Angle to describe the posture for avoiding gimbal lock. Then a constraint model predictive controller is constructed for the multi-variable, nonlinear and coupling model of the robot and the constraints of the environment. Meanwhile, the temporal logic formula is used for describing the complex welding tasks and reducing the workload of repeated programming. Next the expectation values and constraints are converted by the temporal logic formula will be sent to the predictive controller one by one. Finally, the simulation result shows that the system can effectively solve the problem of motion planning for the welding dual-arm robot with gantry.

With the increasing popularity of the wireless network, the security issue for mobile users could be even more serious than it can be expected. Here it is need to search for new architecture and mechanisms to protect the wireless networks and mobile computing application. This paper focuses on intrusion detection and security consideration in wireless local area networks (WLANs) and also presents intrusion detection for WLANs, which gives a wireless intrusion detection system and its architecture consideration. A wireless IDS is similar to a standard, wired IDS, but has additional deployment requirements as well as some unique features specific to WLAN intrusion and misuse detection. Meanwhile, we discuss some issues with wireless networks and Intrusion detection solution to wireless networks.

Many network security applications such as Intrusion Detection System (IDS), Firewall and Data Loss Prevention System (DLPS) are based on deep packet inspection, in this packets header as well as payload of the packets are checked with predefined attack signature to identify whether it contains malicious traffic or not. To perform this checking different pattern matching methods are used by NIDS. The most popular method to implement pattern matching is to use of Finite Automata (FA). Generally, regular expressions are used to represent most of the attack signatures defined by NIDS. They are implemented using finite automata, which takes the payload of packet as input string. However, existing approaches of Finite Automata (FA), both deterministic finite automata (DFA) and non-deterministic finite automata (NFA) for pattern matching are having their own advantages and some drawbacks. The DFA based pattern matching methods are fast enough but require more memory. However, NFA based pattern matching methods are comparatively takes less memory but the speed of matching is very slow, to overcome these drawbacks of finite automata there are many approaches have been proposed. This paper discuses comparative study of some Finite Automata (FA) based techniques for pattern matching in network intrusion detection system (NIDS).

We present a tableau-based algorithm for obtaining an automaton from a temporal logic formula. The algorithm is geared towards being used in model checking in an “on-the-fly” fashion, that is the automaton can be constructed simultaneously with, and guided by, the generation of the model. In particular, it is possible to detect that a property does not hold by only constructing part of the model and of the automaton. The algorithm can also be used to check the validity of a temporal logic assertion. Although the general problem is PSPACE-complete, experiments show that our algorithm performs quite well on the temporal formulas typically encountered in verification. While basing linear-time temporal logic model-checking upon a transformation to automata is not new, the details of how to do this efficiently, and in “on-the-fly” fashion have never been given.

Temporal logic query checking was first introduced by W. Chan in order to speed up design understanding by discovering properties not known a priori. A query is a temporal logic formula containing a special symbol ?/sub 1/, known as a placeholder. Given a Kripke structure and a propositional formula /spl phi/, we say that /spl phi/ satisfies the query if replacing the placeholder by /spl phi/ results in a temporal logic formula satisfied by the Kripke structure. A solution to a temporal logic query on a Kripke structure is the set of all propositional formulas that satisfy the query. Query checking helps discover temporal properties of a system and, as such, is a useful tool for model exploration. In this paper, we show that query checking is applicable to a variety of model exploration tasks, ranging from invariant computation to test case generation. We illustrate these using a Cruise Control System. Additionally, we show that query checking is an instance of a multi-valued model checking of Chechik et al. This approach enables us to build an implementation of a temporal logic query checker, TLQSolver, on top of our existing multi-valued model checker /sub /spl chi//Chek. It also allows us to decide a large class of queries and introduce witnesses for temporal logic queries-an essential notion for effective model exploration.

We demonstrate the first Recurrent Neural Network architecture for learning\nSignal Temporal Logic formulas, and present the first systematic comparison of\nformula inference methods. Legacy systems embed much expert knowledge which is\nnot explicitly formalized. There is great interest in learning formal\nspecifications that characterize the ideal behavior of such systems -- that is,\nformulas in temporal logic that are satisfied by the system's output signals.\nSuch specifications can be used to better understand the system's behavior and\nimprove design of its next iteration. Previous inference methods either assumed\ncertain formula templates, or did a heuristic enumeration of all possible\ntemplates. This work proposes a neural network architecture that infers the\nformula structure via gradient descent, eliminating the need for imposing any\nspecific templates. It combines learning of formula structure and parameters in\none optimization. Through systematic comparison, we demonstrate that this\nmethod achieves similar or better mis-classification rates (MCR) than\nenumerative and lattice methods. We also observe that different formulas can\nachieve similar MCR, empirically demonstrating the under-determinism of the\nproblem of temporal logic inference.\n

In this paper, the problem of synthesizing a hybrid controller for a specification expressed as a temporal logic formula φ is considered. We propose a hierarchical approach which consists of three steps. First, the plant to be controlled is abstracted to a fully actuated system. Using the notion of approximate simulation relation, we design a continuous interface allowing the plant to track the trajectories of its abstraction with a guaranteed precision δ. The second step, which is also the main contribution of this paper, consists in deriving a more robust specification φ′ from the temporal logic formula φ such that given a trajectory satisfying φ′, any other trajectory remaining within distance δ satisfies φ. Third, we design a hybrid controller for the abstraction such that all its trajectories satisfy the robust specification φ′. Then, the trajectories of the plant satisfy the original specification. An application to the control of a second order model of a planar robot in a polygonal environment is considered.

This paper presents a correct and complete algorithm that translates propositional linear time temporal logic (PTL) formulae to event-based automata for finitary control synthesis. It proposes the translation algorithm as a specification interface to well-established automata-theoretic control synthesis methods for discrete-event systems (DES’s). This allows control requirements to be more easily described and understood in an expressive and readable language that temporal logic is widely recognized as. Adding such a translation interface effectively combines specifiability and readability in temporal logic with prescriptiveness and computability in automata. The former temporal logic features support specification while the latter automata features support the prescription of DES dynamics and algorithmic computations. A practical implementation of the interface has been developed, providing an enabling technology for writing more readable control specifications in PTL that it translates for finitary control synthesis in automata. A simple example illustrates the use of the proposed temporal logic interface. Practical implications of the complexity of the translation algorithm are discussed.

In our earlier work, we introduced a state-based approach for the diagnosis of repeatedly occurring failures in discrete event systems (DESs). Since temporal logic provides a simpler way of specifying system properties, in this paper a temporal logic based approach for diagnosing the occurrence of a repeated number of failures is developed. Linear-time temporal logic (LTL) formulae are used to represent the specifications of DESs. Notions of pre-diagnosability for failures and diagnosability for repeated failures are introduced in the setting of temporal logic. A polynomial algorithm for the test of pre-diagnosability for failures is provided. The diagnosis problem for repeated failures in the temporal logic setting is reduced to one in a state-based setting, and so the prior results of state-based repeated failure diagnosis can be applied.