An iterative interference canceller with log-likelihood ratio compensation for LDPC coded MIMO systems

The written-in errors in bit patterned media recording (BPMR) system cause the erroneous bits during the writing process leading to the performance degradation. In this work, we propose the pattern-dependent modified log-likelihood ratio (LLR) usage in low-density parity check (LDPC) decoder to reduce the written-in errors and also improve the write margin. Unlike the existing works, LLR computed based on the input data patterns is used at the LDPC decoder for the cascaded written-in error channel (WEC) with the additive white Gaussian noise (AWGN) channel. The proposed LDPC decoder outperforms the one with conventional LLR in terms of both the write margin, when the SNR is fixed at 5.5 dB, and the performance of LDPC decoder. The SNR gain is about 0.2 dB at the BER of 10- 6.

In previous works, density evolution schemes have been used to design an irregular low-density parity-check (LDPC) code for the multi-input multi-output (MIMO) systems. However the code design based on the density evolution can be used only for simple code structure like LDPC codes and repeat-accumulate (RA) codes. Recently simple and accurate irregular LDPC code design method based on the extrinsic information transfer (EXIT) chart was introduced for an AWGN channel. This code design scheme is much flexible, therefore it can be used for any kind of code structure like turbo codes. In this paper we design an irregular LDPC code for a MIMO system using the EXIT chart based scheme. The EXIT charts are used to obtain the optimal edge degree distribution of the irregular LDPC code combined with the MMSE-SIC MIMO detector. This scheme can be generalized for designing the optimal iterative MIMO detector combined with any kind of channel codes including turbo codes.

This paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. This architecture exploits the iterative decomposition of check-node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. The proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of $10 -^{6}$ between 2 to 4 dB of bit-energy to noise-power-spectral-density $(\mathrm{E}_{b}/ \mathrm{N}_{0})$ with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. The VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).

Low-density parity-check (LDPC) codes have been widely used for Forward Error Correction (FEC) in wireless networks because they can approach the capacity of wireless links with lightweight encoding complexity. Although LoRa networks have been developed for many applications, they still adopt simple FEC codes, i.e., Hamming codes, which provide limited FEC capacity, causing unreliable data transmissions and high energy consumption of LoRa nodes. To close this gap, this paper develops LLDPC, which realizes LDPC coding in LoRa networks. Three challenges are addressed. 1) LoRa employs Chirp Spread Spectrum (CSS) modulation, which only provides hard demodulation results without soft information. However, LDPC requires the Log-Likelihood Ratio (LLR) of each received bit for decoding. We develop an LLR extractor for LoRa CSS. 2) Some erroneous bits may have high LLRs (i.e., wrongly confident in their correctness), significantly affecting the LDPC decoding efficiency. We use symbol-level information to fine-tune the LLRs of some bits to improve the LDPC decoding efficiency. 3) Soft Belief Propagation (SBP) is typically used as the LDPC decoding algorithm. It involves heavy iterative computation, resulting in a long decoding latency, which prevents the gateway from sending timely an acknowledgment. We take advantage of recent advances in graph neural networks for fast belief propagation in LDPC decoding. Extensive simulations on a large-scale synthetic dataset and in-filed experiments reveal that LLDPC can extend the lifetime of the default LoRa by 86.7% and reduce the decoding latency of the SBP algorithm by 58.09×.

In wireless communication, multiple signals are utilized to receive and send information in the form of signals simultaneously. These signals consume little power and are usually inexpensive, with a high data rate during data transmission. An Multi Input Multi Output (MIMO) system uses numerous antennas to enhance the functionality of the system. Moreover, system intricacy and power utilization are difficult and highly complicated tasks to achieve in an Analog to Digital Converter (ADC) at the receiver side. An infinite number of MIMO channels are used in wireless networks to improve efficiency with Cross Entropy Optimization (CEO). ADC is a serious issue because the data of the accepted signal are completely lost. ADC is used in the MIMO channels to overcome the above issues, but it is very hard to implement and design. So, an efficient way to enhance the estimation of channels in the MIMO system is proposed in this paper with the utilization of the heuristic-based optimization technique. The main task of the implemented channel prediction framework is to predict the channel coefficient of the MIMO system at the transmitter side based on the receiver side error ratio, which is obtained from feedback information using a Hybrid Serial Cascaded Network (HSCN). Then, this multi-scaled cascaded autoencoder is combined with Long Short Term Memory (LSTM) with an attention mechanism. The parameters in the developed Hybrid Serial Cascaded Multi-scale Autoencoder and Attention LSTM are optimized using the developed Hybrid Revised Position-based Wild Horse and Energy Valley Optimizer (RP-WHEVO) algorithm for minimizing the "Root Mean Square Error (RMSE), Bit Error Rate (BER) and Mean Square Error (MSE)" of the estimated channel. Various experiments were carried out to analyze the accomplishment of the developed MIMO model. It was visible from the tests that the developed model enhanced the convergence rate and prediction performance along with a reduction in the computational costs.

Summary form only given. The ultimate performance limit or threshold of low-density parity-check (LDPC) codes is close to capacity over various memoryless channels (S.-Y. Chung, IEEE Trans. Info. Theory, vol. 47, pp. 657-670, 2001). Since the capacity of binary-input partial response (PR) channels is unknown, we estimate the capacity by calculating the threshold of capacity-approaching LDPC codes over these channels. We assume a BCJR equalizer for the channel and a sum-product message-passing decoder for the LDPC code. We also assume that the log-likelihood ratios (LLRs) in the channel BCJR and the LDPC decoder are Gaussian. We use our results to guide the design of decoder schedules that minimize the number of computationally expensive BCJR steps. The threshold calculation method can be used to optimize the left and right degree sequences of the LDPC code factor graph, using fast linear programming methods, to provide better thresholds than regular codes.

Low Density Parity Check (LDPC) are the linear error correction codes for amendment of mistakes, a technique of transmitting the messages over the noisy channel. With lieu- Shannon’s controlled implementation and typically parallel execution of plan, low-density parity check codes are mainly executed at enquire and well-designed area of applications. Bipartite graph is used for development of LDPC codes. LDPC being limit stirring in the direction of codes which means its actual building exists that enables outer edge to be closely intended for symmetry of a channel with no memory. FPGA or Field Programmable Gate Array is based on configurable logic block (CLB) and is a semiconductor gadget that is associated by virtue of programmable interconnects. FPGAs are highly robust and can be created or designed as per the application or usefulness prerequisite of application. This research paper presents adaptable and more compatible LDPC decoder in change for other general LDPC decoder. This decoder has a completely adaptable LDPC plan in FPGA, which supports distinct codes and rate of information. The design is implemented in Xilinx ISE 14.2 software using VHDL programming and synthesized on SPARTAN 3E FPGA. Keywords: Sparse bipartite graph, threshold, Shannon limit, Very High Speed Integrated Circuit Hardware Description Language (VHDL) Cite this Article Sachit Gupta, Richa, Adesh Kumar. FPGA Implementation of LDPC Codes. Journal of Telecommunication, Switching Systems and Networks . 2018; 5(1): 21–28p.

최근 대용량, 초고속 통신 서비스의 비중이 높아짐에 따라 배열 안테나를 사용하는 MIMO(Multi-Input Multi-Output) 시스템의 활용이 중요하게 평가되고 있다. 하지만 기존의 MIMO 시스템은 다수의 안테나를 사용하기 때문에 안테나의 개수만큼 RF(Radio Frequency) 체인이 요구되며, 이로 인해 복잡도와 전력 소모가 크다는 단점을 가진다. 이러한 기존 MIMO 시스템의 단점을 해결하기 위해서 단일 능동 소자와 다수의 기생 소자를 이용하는 방식의 ESPAR(Electronically Steerable Parasitic Array Radiator) 안테나를 사용하는 빔 공간 MIMO 시스템에 대한 연구가 활발히 진행되고 있다. ESPAR 안테나를 사용하는 빔 공간 MIMO 시스템은 단일 RF 체인으로 구성되어 있기 때문에 기존 MIMO 시스템의 단점을 해결할 수 있다. 본 논문에서는 시스템의 보안성을 향상시키기 위해 QPSK(Quadrature Phase Shift Keying) 변조 방식의 ESPAR 안테나를 사용하는 빔 공간 MIMO 시스템에 비예측성, 비주기성, 구현의 용이성, 민감한 초기조건 등의 특징을 가지고 있는 카오스 통신 알고리즘을 적용하여 QPSK 변조 방식의 ESPAR 안테나를 사용하는 카오스 빔 공간 MIMO 시스템을 구성하고 성능을 평가한다. Recently, utilization of MIMO(Multi-Input Multi-Output) system using array antennas is evaluated significantly according to the extension of high-capacity and high-speed communication services. However, MIMO system has disadvantages such as high-complexity and high-power-consumption, because RF(Radio Frequency) chain is required as antenna number, and several array antenna is used in conventional MIMO system. In order to solve these problems, research about beamspace MIMO system using ESPAR(Electronically Steerable Parasitic Array Radiator) antenna that has single RF chain by using one active antenna and several parasitic elements has been studied actively. Beamspace MIMO system using ESPAR antenna is possible to solve the problems of conventional MIMO system, because this system is composed by single RF chain. In this paper, in order to improve the system security, chaos communication algorithm that has characteristics such as non-periodic, non-predictability, easy implementation and initial condition is applied to QPSK (Quadrature Phase Shift Keying) modulated beamspace MIMO system. We design the chaos QPSK modulated beamspace MIMO system, and evaluate SER performance of this system.

Partially parallel decoding architectures are widely used in the design of low-density parity-check (LDPC) decoders, especially for quasi-cyclic (QC) LDPC codes. To comply with the code structure of parity-check matrices of QC-LDPC codes, many small memory blocks are conventionally employed in this architecture. The total memory area usually dominates the area requirement of LDPC decoders. This paper proposes a low-complexity memory access architecture that merges small memory blocks into memory groups to relax the effect of peripherals in small memory blocks. A simple but efficient algorithm is also presented to handle the additional delay elements introduced in the memory merging method. Experiment results on a rate-1/2 parity-check matrix defined in the IEEE 802.16e standard show that the LDPC decoder designed using the proposed memory access architecture has the lowest area complexity among related studies. Compared to a design with the same specifications, the decoder implemented using the proposed architecture requires 33% fewer gates and is more power-efficient. The proposed new memory access architecture is thus suitable for the design of low-complexity LDPC decoders.

This paper investigates the detection schemes for single-carrier underwater acoustic communications over the severe time-dispersive channels. A low-density parity-check (LDPC) code is employed for the improvement of the equalization performance. A detection scheme with Turbo conception is proposed which includes a LDPC decoder in the feedback loop of an iterative block decision feedback equalizer (IB-DFE), combining the iterative frequency domain equalization of IB-DFE with the iterative LDPC decoding. The external messages are fully exchanged between the IB-DFE and the decoder during the processing of the joint iterative equalization and decoding. The numerical results demonstrate that the decision signals with higher reliability from the LDPC decoder accelerate the convergence of the equalizer and enhance the detection performance, yielding up to 6 dB performance gains when compared with the scheme without LDPC code. Compared with the concatenated scheme in which the process of the iterative frequency domain equalization is serial concatenated with that of the iterative LDPC decoding, the combined scheme obtains about 2 dB performance gains.

Transmit diversity schemes have been studied for high spectral-efficiency and high bit-rate transmission, such as multi-input multi-output (MIMO) systems. In this paper, a novel dual polarized ceiling-mounted antenna is designed and simulated. In the MIMO systems, forward error correction coding is essential for high quality communications. At the two typical scenes, the single-input single-output system compared with two single polarized antennas and an dual polarized antenna MIMO system is tested. It is shown that the MIMO system have improved throughput level obviously. The dual polarized ceiling-Mounted dual streams MIMO antenna will save much construction cost in the long-term evaluation systems in the future, which can be called the “green” MIMO antenna.

Recently, in multi-way relay systems employing physical-layer network coding (PNC), channel condition-based pair selection for pairwise information exchange has drawn increased attention as it provides improved performance over the alternative approaches such as round-robin scheduling of node pairs. With pairwise information exchange, there is additional time diversity available due to transmission of the same coded information block of most of the nodes twice in two adjacent time slots. This additional time diversity can be exploited to further enhance the system performance by means of joint channel decoding-network coding. To this end, a joint belief propagation (BP)-based channel decoding-network coding algorithm was proposed by us in [9] for the relay node of low density parity check (LDPC)-coded multi-way relay systems. Even though the algorithm of [9] offers much superior performance over separate channel decoding, it is highly computational expensive and may not be suitable for applications in wireless sensor networks. Alternatively, bit-flipping (BF)-based LDPC decoding can be adopted at much lower computational complexity. In this paper, we develop a low complexity joint bit-flipping (BF)-based channel decoding and network coding algorithm for LDPC-based multi-way relay systems. The BER performance of the proposed algorithm is investigated using computer simulation for two commonly used LDPC codes. The simulation results demonstrate that superior BER performance can be achieved using the proposed joint decoding algorithm over separate and independent bit-flipping-based LDPC channel decoding at the relay. The simulation results also verify that our proposed algorithm is capable of harnessing the aforesaid additional time diversity available. Though the performance of the proposed joint decoding algorithm is inferior to the BP-based algorithm of [9], due to its low computationally complexity, this algorithm may be appealing for applications in relay nodes with low computational capabilities and memory constraints.

The joint Viterbi detector/decoder (JVDD) has been proposed as an alternative to the powerful and ubiquitous low-density parity check (LDPC) coding schemes, that are used in the majority of channel coding applications today. At shorter block lengths, the JVDD is able to outperform the state-of-the-art LDPC decoder that can be found in many of today’s systems, from deep-space communications to the digital video broadcasting standard, to the advanced television standard committee 3.0. Researchers have developed the tools to analyze the performance of the LDPC decoder, which is known as the sum-product algorithm or message passing algorithm. These tools include density evolution (DE) and extrinsic information transfer (EXIT) charts. To date, no similar such analysis exists for the JVDD. In the current paper we perform a similar preliminary analysis on the JVDD algorithm akin to what DE and EXIT charts are for the LDPC decoder. The current new analysis of the JVDD allows prediction of its probability of error based on the probability distribution functions of the metrics used within the algorithm. Our analysis plays a similar role to the abovementioned tools developed for the LDPC decoder: it allows us to predict the performance of the JVDD under various conditions (such as varying SNR’s, thresholds, and block lengths), it improves our understanding of the JVDD algorithm and the match against Monte-Carlo simulations verifies our assumptions on the main error-causing mechanisms within the JVDD.

Multiple input multiple output (MIMO) system is one of the most promising wireless technologies that can achieve wide coverage, high throughput and improved reliability. Low density parity check (LDPC) codes can achieve capacity near Shannon's limit with good error correcting performance. In this paper, we combined LDPC codes with orthogonal space time block codes (OSTBC) in MIMO systems. The performance of LDPC codes depends on the structure of the parity check matrix and decoding algorithms. In this paper, we analyzed the bit-error rate (BER) performance of different LDPC codes like Quasi Cyclic (QC) and random which differs in their parity check matrix structures. For low complexity decoding, log domain Sum Product Algorithm (log-SPA) is used which has messages in the form of log-likelihood ratios (LLR). Further, the approximate BER expressions are derived and verified for above mentioned system with different antenna configurations.

Low-density parity-check (LDPC) codes are widely used in many radio systems due to its superior performance and Software Defined Radio (SDR) is an emerging paradigm of the wireless communication system design due to its good flexibility and adaptability. However, LDPC decoding is computationally intensive and the implementation of it on software in a parallel way is quite challenging due to the characteristics of LDPC decoding and structures of software. In this paper, we presented an efficient software implementation of the LDPC decoder using the Parallel Code Block Decoding mode for the WiMAX SDR base band system on IBM CELL Broadband Engine (BE). With a single Synergistic Processor Element (SPE) running at 3.2GHz, the implemented LDPC decoder can achieve a throughput up to 1.71 Mbps. With eight SPEs working in parallel, the decoder can obtain the throughput more than 13Mbps, which can meet the WiMAX system requirement at 5MHz bandwidth mode.