An Overview of Digital Image Processing and Recognition (Invited Paper)

Image processing and recognition methods are useful in many fields. According to situation, different techniques are used. For many years, methods based on optical Fourier transformation were very popular. Image recognition was performed generally by using optical correlators. Correlation techniques were strongly developed especially for military applications, but in many cases (industrial, biological and biomedical applications) these techniques suffer from a number of limitations. For these reasons, methods based on extraction and statistical processing of image features are more useful. Set of features can be extracted directly from an image (features based on image morphology, image moments etc.) or from image transforms (Fourier, Radon, Hough, Sine, Cosine etc.). The Fourier transformation is one of the most important in image processing. It can be simply performed by using an optical diffractometer. It allows to build image descriptors independent on image translation and after processing independent on image rotation. Diffractometers are very convenient in industrial and medical applications. Digital image processing and recognition were strongly developed on powerful workstations, however these procedures can also be implemented in PCs with DSP microprocessor cards or in situations where digital transforms used for image processing can be simply implemented and do not consume a lot of time. The example of biomedical image recognition performed in an optical way, by using a diffractometer, and in a digital system with a CCD camera will be described here.

Reconfigurable algorithm for digital image processing is now a growing area of research in real time embedded systems. The Edge Detection Algorithms are one of the primary algorithms for object detection through segmentation and extraction in digital image processing. These algorithms are usually used in software but can also be implemented for special purposes in hardware including high processing speed and good accuracy. The limitation of the processor speed affects the software implementation of image processing algorithms. The advances in VLSI technology have solved this. This project uses the Hardware Description Language (HDL) to implement the Sobel edge detection algorithm for Field Programmable Gate Array devices (FPGA) and focuses on the outstanding features of FPGA technology. The analysis shows that the hardware Sobel edge operator implements provide a higher speed than the simulation software. The proposed implementation uses a modified architecture that reduces hardware resources effectively. The images are transmitted through serial UART communication from PC to FPGA computer.

Image processing is an unceasingly growing area with a range of applications including cryptography, medicine, video surveillance, remote sensing, and many more. Implementing sophisticated algorithms to process the large amount of data using software solutions makes the response slower, and that's where hardware implementation comes into the picture. Field Programmable Gate Arrays (FPGAs) are getting popular due to low latency, connectivity, parallel computing, and flexibility. The unique architecture of the FPGA has made it possible to use the technology for applying in many applications to have better and faster results. This paper is aiming at providing a comprehensive survey on the hardware implementations of image processing algorithms to facilitate the improvement in efficiency using FPGAs. The widely used Xilinx PYNQ is also presented in this paper as they play a major role in reducing the development time.

Digital image recognition based on Fractional-order-PCA-SVM coupling algorithm

This book focuses on embedded image processing and, more specifically, on the efficient implementation of image processing algorithms on the TMS320C6000 family of digital signal processors (DSPs) from Texas Instruments (TI). The text is divided into six chapters: "Introduction," "Tools," "Spatial Processing Techniques," "Image Filtering," "Edge Detection and Segmentation," and "Wavelets." The text is supported by two appendices, as well as a CD-ROM. The CD-ROM includes all source code and project files as well as many test images and one text video clip. There is no better way to learn than by example, and the book offers plenty of them. While the book is intended for signal and image processing practitioners or software developers that plan to use a TI DSP, most of the programming techniques demonstrated in the book can easily be applied to other embedded platforms. The book is well written and succeeds in filling a big void in image processing literature, tackling how to efficiently implement signal and image processing algorithms using embedded processors.

The combination of hardware acceleration and flexibility make FPGAs (field programmable gate arrays) important to image processing applications. There is also a need for efficient, flexible hardware/software codesign environments that can balance the benefits and costs of using FPGAs. Image processing applications often consist of pipeline of components where each component applies a different processing algorithm. Components can be implemented for FPGAs or software. Such systems enable an image analyst to work with either FPGA or software implementations of image processing algorithms for a given problem. The pipeline assignment problem chooses from alternative implementations of pipeline components to yield the fastest pipeline. Our codesign system solves the pipeline assignment problem to provide the most effective implementation automatically, so the image analyst can focus solely on choosing components, which make up the pipeline. However, the pipeline assignment problem is NP complete. An efficient, dynamic solution to the pipeline assignment problem is a desirable enabler of codesign systems which use both FPGA and software implementations. This paper is concerned with solving pipeline assignment in this context. Consequently, we focus on optimal and heuristic methods for fast (fixed time limit) runtime pipeline assignment are investigated. We present experimental finding for pipelines of twenty or fewer components, which show that in our environment, optimal runtime solutions are possible for smaller pipelines and nearly optimal heuristic solutions are possible for larger pipelines.

Demand for implementation of image processing algorithm on FPGA is exponentially increases in the present world. Many research works is carried for image processing applications and implementation on FPGA. Nowadays identification, classification, and recognition of an object in the highly sophisticated regions are big challenge. Tracking intended object in the congestion region is very difficult. CCTV is used to detect and track the object in the traffic regions. Sometimes it gives false alarm by capturing shadows due to change in the intensity levels in the dynamic background. In this paper an efficient background circuit is developed to detect the object in the dynamic/static background to avoid false alarm. The real time captured image is processed by the proposed background circuit, and it is implemented on FPGA. It has been observed that the result obtained from this proposed work is good in terms of processing time and area utilization.

Remarks on Hardware Implementation of Image Processing AlgorithmsImage processing in industrial vision systems requires both real-time speed and robustness. Modern computers, which fulfill the first demand, are sensitive to hard industrial environment conditions and require considerable amounts of energy. Programmable logic chips are available, which can realize many simple, still time-consuming operations in a parallel or a pipelined manner. The paper discusses particular features of the pipelined architecture and presents selected techniques of implementing early image processing procedures in hardware.

A Landsat image of the multispectral scanner system covering an area lying between the Aqabah Gulf and the southern margin of the Dead Sea was analyzed by digital image processing techniques to delineate various geological and structural features of southwest Jordan area. Two major techniques in digital image processing were employed. They are preprocessing and enhancement, and their constituent treatment processes. Types of lithology, lineaments and topographic contrasts of southwest Jordan were used as test criteria. Results of comparison indicate that the combination of images processed by first principal component, second principal component and filtered first principal component as assigned to the hue, saturation and intensity system coordinates, respectively, provided better results than products of other digital techniques. Such good results enable geologists to map major lithologies, lineaments and other structural features effectively, as well as to assess topographic variations.

Based on chaos synchronization of two response lasers (RLs) injected by the common chaos signals from a driving laser (DL) with double optical feedback (DOF) and an additional neural network (NN), a bidirectional chaotic secure communication system with machine learning capability is proposed and the long-distance digital image transmission and recognition performances are numerically investigated. The simulated results show that the time delay signature (TDS) of the driving chaotic signals from DL with DOF is greatly weakened under suitable operation conditions. Two RLs can generate chaos signals with low TDS and broad bandwidth, and the high-quality chaos synchronization between two RLs can be achieved while the synchronization quality between DL and any one of RLs is extremely bad, which is helpful to realize the secure communication. Using the synchronized chaos output signals from two RLs as chaos carriers and chaos masking (CM) encoding method, the bidirectional 10 Gb/s secure communication over 140 km fiber channel can be realized and the effects of the fiber parameters on the communication performances are discussed. After adopting an additional NN, a long-distance digital image transmission and recognition based on this proposed secure communication system can be realized and the communication distance can be extended to 220 km.

With the rapid development of digital image processing and recognition, the intelligent grid wins a great opportunity. We could be able to get the information from digital images quickly based on computer analysis, algorithms of deep learning and machine learning, grid data extraction, model training and image recognition. The article firstly reviewed the current status of traditional grid, including a broad overview of the specific strengths and weaknesses, secondly analyzed the intelligence algorithms of deep learning and machine learning based on neural network, then achieved the recognition and reconstruction of wiring diagram through image recognition based on neural network, lastly showed the prospects of image recognition in power system.

In this study, dimensions, mass and shape characteristics of five commercial loquat cultivars (‘Akko XIII’, ‘Champagne de Grasse’, ‘Guzelyurt 6’, ‘Hafifcukurgobek’ and ‘Sayda’) and two genotypes (‘KKTC3’ and ‘KKTC4’) were determined. Physical properties such as dimension and shape were determined both by digital caliper and image processing to compare each other. Among the cultivars and genotypes tested, ‘KKTC4’ (58.88 mm) had the highest length while ‘KKTC3’ had the highest major diameter, minor diameter, mass, geometric mean diameter, surface area and volume, with a mean of 46.31 mm, 43.61 mm, 60.12 g, 48.69 mm, 74.82 cm2, and 61.25 cm3, respectively. The greatest value of elongation and the smallest value of sphericity were obtained from ‘Akko XII’ with 1.33, and ‘Akko XII’ was more oblong than the other cultivars and genotypes. The smallest value of elongation and the greatest value of sphericity were obtained from ‘Sayda’ with 1.12 and 91.16%, respectively. The results of comparison between the digital caliper and image processing showed that using the image processing method could potentially be rapid and alternative to the conventional measurement method. Key words: Eriobotrya japonica, image processing, loquat, physical properties.

Design of Systems-on-Chip has become very common especially with the remarkable advances in the field of high-level system modeling. In recent years, Matlab also offers a Simulink interface for the design of hardware systems. From a high-level specification, Matlab provides self-generation of HDL codes and/or FPGA configuration codes while providing other benefits of easy simulation. In addition, a large part of the Systems-on-Chip use at least one image processing algorithm and at the same time border detection is one of the most used algorithms. This paper presents a study and a hardware implementation of various algorithms of borders detection realized under Xilinx System-Generator. The various algorithms are implemented using Xilinx FPGA device, the simulation and synthesis results are also compared. We use the Xilinx Zed-Board for physical implementations in-the-loop.

Real-time image processing is one of the fundamental elements in achieving IR 4.0. The rapid development of digital image processing techniques has enabled various applications in fields such as healthcare, transportation, and manufacturing. People are seeking higher-performance image processing as traditional image processing is no longer fulfilling the demands. FPGA-based digital image processing has become one of the choices for the public due to its parallel pipelining, which enables shorter processing time and better performance. Several digital image processing algorithms have been developed in this project, which are gray level transformation, brightness manipulation, contrast adjustment, thresholding, and inversion. They are the most popular algorithms used in digital image processing. Microsoft Paint is used to convert the format of the color input image to bitmap format, followed by MATLAB to convert it into a hexadecimal file to be read and written in FPGA. Platforms such as ModelSim Altera and Intel Quartus II are used to write Verilog HDL for digital image processing algorithms. As a result, five hexadecimal files are obtained from the simulation. The output hexadecimal files are further processed in MATLAB to generate respective images.

The decreasing cost of computing power and the introduction of low cost imaging boards justifies the increasing number of applications of digital image processing techniques in the area of biomedicine. There is however a large software gap to be fulfilled, between the application and the equipment. The requirements to bridge this gap are twofold: good knowledge of the hardware provided and its interface to the host computer, and expertise in digital image processing and analysis techniques. A software package incorporating these two requirements was developped using the C programming language, in order to create a user friendly image processing programming environment. The software package can be considered in two different ways: as a data structure adapted to image processing and analysis, which acts as the backbone and the standard of communication for all the software; and as a set of routines implementing the basic algorithms used in image processing and analysis. Hardware dependency is restricted to a single module upon which all hardware calls are based. The data structure that was built has four main features: hierchical, open, object oriented, and object dependent dimensions. Considering the vast amount of memory needed by imaging applications and the memory available in small imaging systems, an effective image memory management scheme was implemented. This software package is being used for more than one and a half years by users with different applications. It proved to be an efficient tool for helping people to get adapted into the system, and for standardizing and exchanging software, yet preserving flexibility allowing for users' specific implementations. The philosophy of the software package is discussed and the data structure that was built is described in detail.