Analog Design and Machine Learning: A Review

In this paper, we evaluate the noise performance of future nano-scale MOSFETs fabricated using strain engineering technique, channel engineering with III-V materials, and quantum-well structures for low noise, low power radio-frequency (RF), analog and mixed-signal integrated circuit (IC) designs. We conduct this study utilizing our recently defined equivalent noise sheet resistance. We present the experimental results for devices fabricated in UMC's 65 nm, 40 nm and 28 nm CMOS technology nodes and other recently published results down to the 18 nm technology node.

Since scaling of CMOS is reaching the nanometer area serious limitations enforce the introduction of novel materials, device architectures and device concepts. Multi-gate devices employing high-k gate dielectrics are considered as promising solution overcoming these scaling limitations of conventional planar bulk CMOS. Variation Aware Analog and Mixed-Signal Circuit Design in Emerging Multi-Gate CMOS Technologies provides a technology oriented assessment of analog and mixed-signal circuits in emerging high-k and multi-gate CMOS technologies.

The Electronic Design Automation (EDA) tools have achieved high degree of maturity and reliability over the years for digital design. The design of analog circuits is a challenge attributed to the existence of multi-dimensional tradeoffs among multiple analog performance metrics like gain, bandwidth, power dissipation, supply voltage, input/output impedances, linearity, voltage swings and noise. The analog design proves to be a significant bottleneck in a System on Chip (SoC) implementation due to lack of automation techniques. To address this issue, the algorithms of the functioning of human brain or soft computing techniques can be gainfully deployed. This work proposes an integrated MaxFit Genetic Algorithm (GA) and GA-SPICE framework to achieve multi-objective optimization of analog design automation. The design of two-stage op-amp is demonstrated in this framework to optimize the objectives of open-loop DC gain, phase margin, unity gain-bandwidth, slew rate, power dissipation and area. The design is performed by proposed MaxFit GA programming of op-amp design equations in MATLAB environment and the design is transmitted seamlessly to LTspice to perform SPICE simulations for design verification. The dynamic fitness evaluation on SPICE generated performance metrics at each iteration of GA programming by transmitting them to MATLAB environment enhances the robustness of analog design significantly.

With this issue, we celebrate our 20th Anniversary! We started our first issue back in 1991. The journal appeared quarterly for a couple of years then bi-monthly for a while and since 1997 it appears monthly and on-line since 1999. Our journal is the only publication devoted exclusively to analog Integrated circuits (ICs) and signal processing research. It is becoming the premiere publication in the fields of analog, radio frequency (RF) and mixed signal IC design and applications. Many of us call it ‘‘the Analog Journal’’ or ‘‘the red and yellow’’! Indeed, the material we publish reflects a very significant portion of analog research conducted in industry, academia and research Labs worldwide. On behalf of the Editorial Board, I would like to thank our authors and reviewers who made the journal what it is today. Special thanks go to the Springer staff for their very dedicated work over the years with the journal or ‘‘ALOG’’ as they call it. Happy 20th Anniversary to ‘‘ALOG’’! and Happy New Year 2011 to you, our readers! We look forward to hearing from you with any suggestions or feedback you may have so we can serve you even better. Mohammed Ismail is a Professor and Founding Director of the Analog VLSI Lab at the Ohio State University, USA and of the RaMSiS Group at KTH, Sweden. He is also affiliated with the ElectroScience Lab at Ohio State. Currently, he conducts research on robust low power RF and mmwave ICs for wireless, bio and multimedia applications with a focus on manufacturable low cost high volume CMOS solutions for mobile and wearable embedded devices. He served as a Corporate Consultant to over 30 companies and is a Co-Founder of Firstpass Technologies, Inc. a developer of RF and mixed signal IPs. He Cofounded ANACAD-Egypt (now part of Mentor Graphics). He advised the work of 49 Ph.D. students and of over 90 M.S. students. He authored or co-authored a dozen books and over 250 journal publications. He is the Founding Editor-in-Chief of the Journal Analog Integrated Circuits and Signal Processing, Springer and the Founder of the IEEE ICECS, the flagship Region 8 conference of the IEEE Circuits and Systems Society. He received the US Presidential Young Investigator Award, the Ohio State Lumley Research Award four times, in 1992, 1997, 2002 and 2007 and the US Semiconductor Research Corporation’s Inventor Recognition Award twice. He is a Fellow of IEEE.

This paper reviews the application of evolutionary computation techniques to analog, mixed-signal and radio-frequency design problems. Design needs, limitations of existing approaches and open challenges are pointed out.

The ”flipped voltage follower (FVF)” is an enhanced buffer cell widely employed for low-power and/or low voltage operation. The applications of the FVF and its variations in analog and mixed signal (AMS) circuit design have increased continuously over the last few years. These are specially promising in deep submicrometer CMOS technology. In 2004 the paper ”The Flipped Voltage Follower: A useful cell for low-voltage low-power circuit design” was published [1], where the most important information about this versatile cell was compiled. Since then, several modifications of the FVF and a wide variety of new applications have been reported. No other article with a similar purpose has been published since then. The aim of this chapter is to make a compendium summarizing some of the most relevant information published to date on the FVF. In order to facilitate AMS designers the utilization of this cell in this chapter we revisit, classify and summarize most applications of the basic FVF and its variations. Although it is tutorial in nature, it can be helpful for those who want to introduce themselves in the study of this cell or for experienced designers who want to become familiar with the principle of operation, improved versions and applications, so that both can exploit to its maximum the potential of the FVF in a wide number of applications or also to develop new ones.

This chapter covers the template-based placement approach proposed in the tool AIDA-L. In short, this Placer first extracts the topological relations described in a XML template file to a non-slicing B*-tree layout representation (Chang et al., Proceedings of the 37th ACM/IEEE Design Automation Conference (DAC), 2000, pp. 458–463). Then, the B*-tree is packed using the modules, which are instantiated from the AIDA’s analog module generator (AIDA-AMG) (Canelas et al., Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, IGI Global, Hershey, PA, 2014), to generate the floorplan that respects the high level floorplan guidelines provided by the designer. The first section of this chapter covers the overall architecture of the template-based Placer, followed, by the description of the high level floorplan guidelines contained in the template file in section “XML Description for Template-based Placement”. The B*-tree layout representation and extraction procedure are properly detailed in sections “B*-Tree Extraction” and “Instantiation: AIDA’s Analog Module Generator”, and also, a brief overview of the instantiation of the modules and the characteristics of the parametric module generator are provided. In section “B*-Tree Packing”, the floorplan packing from the B*-tree layout representation is overviewed, followed, by a simple illustrative case study.

The mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have almost automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills, design cycle time. This paper presents a novel design flow for constrained optimization of nano-CMOS analog circuits. The proposed analog design flow combines polynomial-regression based models and genetic algorithm for fast optimization. For evaluating the effectiveness of the proposed design flow, power minimization in a 50nm CMOS based current-starved voltage-controlled oscillator (VCO) is carried out, while treating oscillation frequency as a performance constraint. Accurate polynomial-regression based models are developed for power and frequency of the VCO. The goodness-of-fit of the models is evaluated using SSE, RMSE and R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Using these models, we form a constrained optimization problem which is solved using genetic algorithm. The flow achieved 21.67% power savings, with a constraint of frequency ≥ 100 MHz. To the best of the authors' knowledge, this is the first study which approaches a VCO design problem as a mathematical constrained optimization involving the usage of regression based modeling and genetic algorithm.

Focusing in 2009 on Adaptive Circuits and Systems, ISSCC will offer four plenary talks, approximately 250 technical papers, nine evening panels and special evening sessions, all included in the registration price. Information about these events and the eight ISSCC 2009 circuit design forums, ten 90-minute tutorials, and an all-day Short Course on Low-Voltage Analog and Mixed-Signal CMOS Circuit Design will be published on the conference website in November.

Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS

Due to the growing complexity and numerous manufacturing variation in safety-critical analog and mixed-signal (AMS) circuit design, rare failure detection in the high-dimensional variational space is one of the major challenges in AMS verification. Efficient AMS failure detection is very demanding with limited samples on account of high simulation and manufacturing cost. In this work, we combine a reversible network and a gating architecture to identify essential features from datasets and reduce feature dimension for fast failure detection. While reversible residual networks (RevNets) have been actively studied for its restoration ability from output to input without the loss of information, the gating network facilitates the RevNet to aim at effective dimension reduction. We incorporate the proposed reversible gating architecture into Bayesian optimization (BO) framework to reduce the dimensionality of BO embedding important features clarified by gating fusion weights so that the failure points can be efficiently located. Furthermore, we propose a conditional density estimation of important and non-important features to extract high-dimensional original input features from the low-dimension important features, improving the efficiency of the proposed methods. The improvements of our proposed approach on rare failure detection is demonstrated in AMS data under the high-dimensional process variations.

Low voltage designs continue to play important roles, as well as creating challenges, in modern analog and mixed-signal integrated circuits (IC) that are expected to operate under low supply voltage. This is either due to the technology scaling into sub-100 nm CMOS, or in the context of low-power battery-operated devices that force the ICs to function less than the nominal supply voltage at the specific technology node [1–13]. Both situations create stringent requirements in analog and mixed-signal IC designs due to low-supply voltage headroom, especially when the supply voltage is lower than the nominal value of that technology, e.g. an analog IC designed in 0.18 μm CMOS must tolerate the reduced voltage headroom of a 1.2 V supply voltage while it cannot benefit from smaller parasitics and higher speed of more advanced CMOS technologies, like 130 or 90 nm.

Noise figure and gain are critical parameters in the design of any product featuring a high-frequency receiver. We present here for the first time a noise and gain characterization of HBTs fabricated in a development version of IBM's new 90 GHz, 0.18 /spl mu/m-generation SiGe BiCMOS process with copper interconnects. At 2 GHz, we report a noise figure of less than 0.4 dB and an associated gain of 14 dB, a significant (0.3-0.5 dB) improvement over prior SiGe and GaAs state of the art in a commercial process. At 10 GHz, we observe a noise figure of 1.45 dB, an approximately 0.7 dB improvement over previous offerings. This performance makes the 0.18 /spl mu/m SiGe BiCMOS technology attractive for RF, analog, and mixed-signal circuit design.

This chapter describes the motivation, scope, and outline of the book. Gallium nitride (GaN) as a wide bandgap material enables compact and efficient power electronics. Since the GaN HEMT a lateral device, the high-voltage GaN switch can be combined with other passive and active devices on the same die. This will enable power management integrated circuits (PMICs) that combine power with sensing and control loop circuits. However, monolithic GaN technology is not yet mature in various aspects including parameter variations and analog performance (matching, etc.). As a main challenge, GaN technology lacks a suitable p-type device. The presented research contributes to the development of solutions for reducing the global electric power consumption as well as the overall cost of offline power converters. The book deals in detail with the following main topics: (1) Introduction into monolithic GaN process technology with a focus on the similarities and differences to traditional silicon technologies. (2) The gate loop challenge with GaN transistors due to tight gate voltage requirements and different approaches to ensure a safe operation. (3) Measurement-based characterization of technology properties for analog, digital, and mixed-signal circuit design. (4) Design and implementation of a monolithic buck converter IC in a 650V e-mode GaN technology. (5) Comparison between the designed GaN-based converter and a commercially available silicon converter based on comprehensive experimental characterization and analysis.KeywordsPower electronicsGaNOffline convertersPersonal electronicsWide bandgapGaN integrationMarket overviewShipping numbersHigh efficiencyGlobal energy consumptionUSB PD

Metal-oxide based bipolar Resistive RAM (RRAM) is one of the most promising candidates for the future non-volatile data storage. Due to unique properties e.g., small footprint, ability to modulate resistance states in wide ranges dynamically, hysteresis and CMOS compatibility, RRAM can be a fruitful candidate for analog circuit design. However, the recent literature only scratches the surface of this interesting prospect. In this paper, a single RRAM behavior is studied under temperature, voltage and process variations from an analog design standpoint. A comparative study is performed between two analog circuits namely, Common Source (CS) amplifier and differential amplifier with traditional passive resistors and with passive resistors replaced by RRAM along with two other design examples, namely constant <inline-formula><tex-math notation="LaTeX">$g_m$</tex-math></inline-formula> biasing circuit and active low-pass filter, where RRAM can be integrated into analog circuits. Our study shows that blind swapping of passive resistors with RRAM in analog circuits can actually degrade the performance metrics. We propose techniques such as usage of RRAM Low Resistance State (LRS) to recover the loss. We also note that hyperbolic I-V characteristics of RRAM can inherently improve the linearity of RRAM based analog designs. Simulation results indicate that RRAM based amplifiers can achieve 2X area reduction, about 1.5X higher bandwidth with only <inline-formula><tex-math notation="LaTeX">$\approx 9\%$</tex-math></inline-formula> reduction in gain. The resistance modulation property of RRAM is applied to realize a source degenerated amplifier with reconfigurable linearity, to a constant transconductance bias circuit to avoid resistance trimming and to design a programmable active low pass filter.