Analysis of read functioning in STT-RAM using adiabatic technique

There is growing interest in emerging non-volatile memory technologies such as Phase-Change Memory, Memristors, and Spin-Transfer Torque RAM (STT-RAM). STT-RAM, in particular, is experiencing rapid development that can be difficult for memory systems researchers to take advantage of. What is needed are techniques that enable designers to explore the potential of recent STT-RAM designs and adjust the performance without needing a detailed understanding of the physics. In this paper, we present the STeTSiMS STT-RAM Simulation and Modeling System to assist memory systems researchers. After providing background on the operation of STT-RAM magnetic tunnel junctions (MTJs), we demonstrate how to fit three different published MTJ models to our model and normalize their characteristics with respect to common metrics. The high-speed switching behavior of the designs is evaluated using macromagnetic simulations. We have also added a first-order model for STT-RAM memory arrays to the CACTI memory modeling tool, which we then use to evaluate the performance, energy consumption, and area for: (i) a high-performance cache, (ii) a high-capacity cache, and (iii) a high-density memory.

Spin-Transfer Torque RAM (STT-RAM) is extensively studied in recent years. Recent work proposed to improve the write performance of STT-RAM through relaxing the retention time of STT-RAM cell, magnetic tunnel junction (MTJ). Unfortunately, frequent refresh operations of volatile STT-RAM could dissipate significantly extra energy. In addition, refresh operations can severely conflict with normal read/write operations and results in degraded cache performance. This paper proposes Cache Coherence Enabled Adaptive Refresh (CCear) to minimize refresh operations for volatile STT-RAM. Through novel modifications to cache coherence protocol, CCear can effectively minimize the number of refresh operations on volatile STT-RAM. Full-system simulation results show that CCear approaches the performance of the ideal refresh policy with negligible overhead.

Energy efficiency has become one of the primary considerations in the designs of cyber-physical systems (CPS). However, CPS with static RAM (SRAM)-based processors suffers from the high leakage power issue of SRAM, thus limiting the energy efficiency of CPS. Recently, Spin-Transfer Torque RAM (STT-RAM) has emerged and been widely regarded as a great alternative as the on-chip memory within processors, owing to STT-RAM's high density and near-zero leakage power characteristics. In addition, recent advances in Magnetic Tunneling Junction (MTJ) technology also realize the multi-level cell (MLC) STT-RAM to further enhance the memory density. Nevertheless, the write disturbance issue greatly limits the energy efficiency of MLC STT-RAM. Even though studies have been proposed to alleviate this issue, most of the previous disturbance reduction strategies could induce additional management overhead by utilizing counters or cause frequent swap operations when the write disturbance happens. Such observations motivate us to propose a simple and effective solution to unify the direct and split mapping cache designs for improving the energy efficiency of MLC STT-RAM. The proposed design is evaluated through a series of experiments on an emulator with encouraging results.

Spin-Transfer Torque RAM (STT-RAM) is extensively studied in recent years. Recent work proposed to improve the write performance of STT-RAM through relaxing the retention time of STT-RAM cell, magnetic tunnel junction (MTJ). Unfortunately, frequent refresh operations of volatile STT-RAM could dissipate significantly extra energy. In addition, refresh operations can severely conflict with normal read/write operations and results in degraded cache performance. This paper proposes Cache Coherence Enabled Adaptive Refresh (CCear) to minimize refresh operations for volatile STT-RAM. Through novel modifications to cache coherence protocol, CCear can effectively minimize the number of refresh operations on volatile STT-RAM. Full-system simulation results show that CCear approaches the performance of the ideal refresh policy with negligible overhead.

Spin-Transfer Torque RAM (STT-RAM) has emerged as a potential candidate for Universal memory. However, there are two challenges to using STT-RAM in memory system design: (1) the intrinsic variation in the storage element, the Magnetic Tunnel Junction (MTJ), and (2) the high write energy. In this paper, we present a physically based thermal noise model for simulating the statistical variations of MTJs. We have implemented it in HSPICE and validated it against analytical results. We demonstrate its use in setting the write pulse width for a given write error rate. We then propose two write-energy reduction techniques. At the device level, we propose the use of a low-M S ferromagnetic material that can reduce the write energy without sacrificing retention time. At the architecture level, we show that Invert Coding provides a 7% average reduction in the total write energy for the SPEC CPU2006 benchmark suite without any performance overhead.

Currently, commercial semiconductor-based memories face the problem of static energy consumption caused by leakage currents. Magnetoelectric random access memory (MeRAM), as a type of nonvolatile memory, provides a solution to this problem and can be used to replace the entire memory hierarchy as a universal memory. In contrast to spin transfer torque RAM (STT-RAM), MeRAM uses voltage controlled magnetic anisotropy (VCMA) effect to manipulate the switching of magnetic tunnel junctions (MTJs). MeRAM or VCMA-MTJ technology is more energy efficient and less likely to break down than STT-RAM. However, VCMA-MTJ suffers from serious write problems caused by variations in the VCMA coefficient, the external in-plane magnetic field, and the CMOS process. In this paper, a compact and SPICE-compatible VCMA-MTJ model is proposed. Then, a self-adaptive write circuit is proposed in which the write process is robust to variations in the VCMA coefficient and the external in-plane magnetic field. Finally, two practical methods are proposed to make our proposed self-adaptive write circuit also robust to 3$\sigma$ CMOS process variations, as demonstrated by Monte Carlo simulations. The proposed self-adaptive write circuit can assist in the design of next-generation high-speed, low-power MeRAM chips.

TAMPER presents a novel write-energy-aware driver circuit to decrease Write Error Rate (WER). Complementary metal-oxide-semiconductor, abbreviated as CMOS are vulnerable to serious shortage in designing parameters such as leakage power, scalability, and vulnerability to soft errors for designing a high dencity circuits. Spin Transfer Torque RAM (STT-RAM) is known as the most promising candidate for replacement the current memory technologies according to non-volatility characteristic. write errors occur in this technology primarily because of the process variation phenomenon. Write errors associated with different current densities is one of the major drawbacks of STT-RAM, also seen elsewhere in similar devices and a possible solution to such is presented and discussed in TAMPER. A thermal assistant write driver circuit is proposed, which has the ability to eliminate the process variation on write operation. By using this thermal assistance the asymmetric behavior of Magnetic Tunneling Junction (MTJ) over writing two states "0" and "1" decrease, which leads to reduce the time and energy needed for the writing operation. Experimental simulations have been done and compared with existing methodologies to validate the design. Power, performance, and WER enhancement by optimization in physical characteristics of transistors is achieved with on average 38.68% improvement of write time latency along with a 1.41% decrease in area.

If spin-transfer torque RAM (SPRAM) technology is used as a true nonvolatile RAM, it will be able to provide normally “off” and instant “on” functions. This would drastically reduce the power consumption of information technology (IT) equipment and its infrastructure while preserving high performance, thus leading to a green IT infrastructure. This paper describes the design issues and solutions for creating a Gb-scale SPRAM; scaling in memory cell current (∝F, F: feature size) and the tunneling magnetoresistive (TMR) device’s write current (∝F2), the maximum voltage applicable to a TMR device (TMR ratio and resistance area product are considered); and the thermal stability of the TMR device (depending on the operation mode and density). Moreover, the cell and array configurations and an indispensable disruptive reading operation are shown for 4F2DDRx compatible operations. SPRAM can cover a system composed of a DRAM region. Finally, the potential of a multibit memory structure that covers the area of a not-and flash memory is discussed.

Comparative analysis of adiabatic logic challenges for low power CMOS circuit designs

We introduce a magnetoelectric junction driven by voltage-controlled magnetic anisotropy (VCMA-MEJ) as a building block for a range of low-power memory applications. We present and discuss specifically two applications, magnetoelectric random access memory (MeRAM) and ternary content-addressable memory (TCAM). The MEJ differs from a magnetic tunnel junction (MTJ) in that electric field is used to induce switching in lieu of substantial current flow in MTJ. Electric field control of magnetism can dramatically enhance the performance of magnetic memory devices in terms of switching energy efficiency and switching speed. The development of such an energy-efficient and ultrafast memory has a potential to change the paradigm of a hierarchical memory system in the conventional computer architecture. By combining speed, low power, and high density, electric-field-controlled magnetic memory merges features of multiple separate memory technologies used in today's memory hierarchy. The performance of a VCMA-MEJs-based MeRAM, especially in the case of one access transistor associated with one MEJ (1T-1R) structure, is evaluated by comparing it with that of phase-change RAM, resistive RAM, and spin transfer torque RAM. MeRAM can achieve ultrafast switching (<1 ns), low switching energy (∼1 fJ), and compact cell size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math>$6\;F^2$</tex-math></inline-formula> with a shared source region, as well as nonvolatility. For another application, we propose the VCMA-MEJ-based TCAM, which will be referred to as MeTCAM, consisting of 4T-2MEJs. Since MeTCAM fully exploits the low power and high density features of the VCMA effect both in write and search operation modes, it obtains a fast searching speed (0.2 ns) with the smallest cell area ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math>$44\;F^2 $</tex-math></inline-formula> ) compared to previous works.

Spin Transfer Torque RAM (STT-RAM) has emerged as a potential candidate for universal memory. The lack of comprehensive electrical modeling for the device is hindering the adaption and design space exploration of the device. In this paper, we investigate the existing models of Spin Transfer Torque — Magnetic Tunnel Junction (STT-MTJ) along with the different implementation tools available (Spice, Verilog-A, Micro-Magnetic Simulator). The study will select the model which most resembles the device's physical parameters including static and dynamic stochastic intrinsic properties. In addition, the selected model is used to investigate several design techniques that can improve power reduction for embedded applications.

Ever larger on-die memory arrays for future processors in CMOS logic technology drives the need for dense and scalable embedded memory alternatives beyond SRAM and eDRAM. Recent advances in non-volatile STT-RAM technology, which stores data by the spin orientation of a soft ferromagnetic material and shows current induced switching, have created interest for its use as embedded memory [1-3]. When a spin-polarized current passes through a mono-domain ferromagnet, it attempts to polarize the current in its preferred direction of magnetic moment. As the ferromagnet absorbs some of the angular momentum of the electrons, it creates a torque that causes a flip in the direction of magnetization in the ferromagnet. This is used in magnetic tunneling junction (MTJ) based spin torque transfer (STT) RAM cells where a thin insulator (MgO) is sandwiched between a fixed ferromagnetic layer (polarizer) and the free layer (storage node). This can be integrated in the metal stack (Fig. 1) and hence provide high memory density. Depending on the direction of the current flow (perpendicular to these layers in our study), the magnetization of the free layer is switched to a parallel (P: low resistance state) or anti-parallel (AP: high resistance state) state. The minimum size cell (mincell) contains an access transistor (Tx) of width 2F (WTX=2F, F: half-pitch of the process node) and a planar storage node of dimensions 2FxF. The area of the mincell is 3Fx2F=6F2. In this paper, we examine the design space for key magnetic material properties and access transistor needed for embedded on-die memory with adequate scalability, density, read/write performance and robustness against various intrinsic variabilities and disturbances. New models and simulation methodologies, calibrated to existing measurements [1], for read, write and disturbance mechanisms are developed. Different storage node structures and materials are evaluated to reveal the most promising scaling options.

The energy consumption issue is efficiently addressed by adiabatic switching technique in design of low power digital circuits. Adiabatic switching technique offers the reducing in energy dissipation during switching events and recycling the load capacitance energy instead of dissipated as heat. But adiabatic circuits highly depend upon power clock and parameter variations. With the help of clocking rule, the digital circuits such as inverter and inverter chain are designed for adiabatic techniques, 2N-2N2P, Efficient Charge Recovery Logic (ECRL), Positive Feedback Adiabatic Logic (PFAL) and Clocked Adiabatic Logic (CAL) using TSPICE simulation. The results show high energy savings as compared to CMOS circuits in specified frequency range.

Power consumption has become a critical concern in both high performance and portable applications. Methods for power reduction based on the application of adiabatic techniques to CMOS circuits have recently come under renewed investigation. In thermodynamics, an adiabatic energy transfer through a dissipative medium is one in which losses are made arbitrarily small by causing the transfer to occur sufficiently slowly. In this work adiabatic technique is used for reduction of average power dissipation. Simulation of 6T SRAM cell has been done for 180nm CMOS technology. It shows that average power dissipation is reduced up to 75% using adiabatic technique and also shows the effect on static noise margin.

The increasing adoption of graphics processing units (GPUs) for high-performance computing raises the reliability challenge, which is generally ignored in traditional GPUs. GPUs usually support thousands of parallel threads and require a sizable register file. Such large register file is highly susceptible to soft errors and power-hungry. Although ECC has been adopted to register file in modern GPUs, it causes considerable power overhead, which further increases the power stress. Thus, an energy-efficient soft-error protection mechanism is more desirable. Besides its extremely low leakage power consumption, resistive memory (e.g., spin-transfer torque RAM) is also immune to the radiation induced soft errors due to its magnetic field based storage. In this article, we propose to LEverage reSistive memory to enhance the Soft-error robustness and reduce the power consumption (LESS) of registers in the General-Purpose computing on GPUs (GPGPUs). Since resistive memory experiences longer write latency compared to SRAM, we explore the unique characteristics of GPGPU applications to obtain the win-win gains: achieving the near-full soft-error protection for the register file, and meanwhile substantially reducing the energy consumption with negligible performance degradation. Our experimental results show that LESS is able to mitigate the registers soft-error vulnerability by 86% and achieve 61% energy savings with negligible (e.g., 1%) performance degradation.