Application of focused ion beam system as a defect localization and root cause analysis tool

Focused ion beam system has been widely used as a critical failure analysis tool as microprocessor technology advances at a ramping speed. It has become an essential step in failure analysis to reveal physical defects post electrical fault isolation. In this highly competitive and challenging environment prevalent today, failure analysis throughput time is of utmost important. Therefore quick, efficient and reliable physical failure analysis technique is needed to avoid potential issues from becoming bigger. This paper will discuss the applications of FIB as a defect localization and root cause determination tool through the passive charge contrast technique and pattern FIB analysis.

As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically, especially for implantation related problems [1] [2]. Implantation related defects, or invisible defects, are the most challenging defect types for the application of fault isolation in all of the failure analysis jobs. The key challenge for these kinds of analyses is to make the defect visible. Sometimes, it is difficult or even impossible to visualize the defective point. Then, sufficient electrical evidence and theory analysis are important to bring the issue to resolution. For these kinds of analyses, a nanoprobing system is a necessary tool to conduct the detailed analysis. Combined with the device physics and electrical theory analysis, nanoprobing can bring out the perfect failure mechanism and problematic process step. There are two popular nanoprobing systems in our lab, one is SEM based and the other is AFM based. Both systems have their advantages and disadvantages in the electrical characterization and fault isolation field. In this paper, an implantation related issue was analyzed. Gross leakage was observed on the failed units as compared with good units. Global fault isolation, TIVA and EMMI failed to find the exclusive hotspot. With the GDS and process analysis, the nanoprobing was employed to the performance check on some of the suspected structures. Finally, the defective location was successfully isolated by nanoprobing. Combined with device physics and electrical analysis, the problematic process was successfully isolated.

The electronic components are the core of all electronic products, the reliability and maintainability directly affect manufacture products quality. And as products become more complex and more demanding. We need more reliable components. In order to solve this problem, we need to analysis how and why those components failed. Failure analysis cases are important data for analysis, data mining and improving reliability. China Electronic Product Reliability and Environment Testing Research Institute (CEPREI) is the earliest research organization engaged in reliability research and failure analysis in China, and has accumulated rich failure case data. By combining data mining methods such as Bayesian network, correlation analysis, we can perform statistical analysis and root cause analysis to assist failure analysis and improve product reliability. This paper will apply the failure analysis case of the electromagnetic relay, and explores and analyses related regular pattern.

PT.XYZ is a manufacturer of body bus which produce four type of bus that is big bus, medium bus, small bus, and mini bus. There is ten process to produce 1 unit big bus that is machine work, sub assembly, pra production, body assembly, metal finish, epoxy, putty, painting, trimming, and PDI (Pre Delivery Inspection). Based on the check sheet data summary from January to August of 2013, most major defect are in the putty process and based on the observation and interviews, there is product defects that pass inspection and entry process of painting. So, this study aims to identify the root cause of the defect and the escape of product defect from inspection. Root Cause Analysis method are used to identify the root cause of this problem. Using Root Cause Analysis method, RCA diagram showed that the root causes of defects are SOP that cannot be applied, the color of paint (epoxy) is less clear for inspection, poor lighting, lack of machinery, the wages of workers, and porous of fiber, while the root cause of the escape of product defect from inspection are SOP that cannot be applied, the color of paint (epoxy) is less clear for inspection, poor lighting, lack of machinery, the wages of workers, and lack of quality standards.

Failure analysis (FA) could provide timely feedback to process optimization and solution paths for system failures; thus, it is critical for the development of advanced driver assistance systems (ADAS). In this chapter, failure analysis flows starting from systems or boards until components or packages and dice are introduced. Electrical fault isolation (FI) techniques designed to locate subtle defects inside complicated semiconductor devices are reviewed. Physical failure analysis approaches adopted to provide artifact free nanometer scale analysis are discussed. Material analysis methods assisting in thorough root cause investigation are presented. Non-destructive and high-resolution imaging tools with the potential of significantly shortening failure analysis through put time are demonstrated. Case studies are used to illustrate strategies and methodologies in ADAS failure analysis.

It is a common perception that electrical fault isolation (EFI) is the heart of a successful integrated circuit failure analysis workflow. Much effort to enhance EFI approaches is vested on improving optical resolution and system signal-to-noise in order to meet performance demands of advanced technologies. In fact, pre- and post-EFI data processing procedures are equally important and capable to influence the success of fault localization significantly. We describe three different analytical workflows applied on actual SOC memory failures to demonstrate this importance.

We report on the use of Fresnel lenses in the failure analysis (FA) of actual failures. The design parameters affecting the performance of Fresnel lenses in terms of resolution, magnification, and field of view have been analyzed. It is demonstrated that the magnification depends linearly on the change in focus distance caused by the lens, normalized by the silicon thickness. The focus distance shift that can be obtained with the Fresnel lens is observed to saturate, whose root-cause remains to be investigated. The field of view is shown to increase with the silicon thickness and, to a lesser extent, with the number of lens rings. It has also been shown that these lenses are robust against patterning distortions. The OBIRCh responses of actual device failures before and after lens placement have been compared, demonstrating clearly the increase in magnification, resolution, and the ability to focus light which all translate into a better electrical fault isolation. All in all, this study proves the usefulness of Fresnel lenses for FA purposes and offers clear guidelines that will facilitate proper lens design.

There are many types of large-scale complicated equipments in process industry. Accidents caused by faults of these equipments always lead to serious consequences. Fault diagnosis and root cause tracing based on FMEA and FTA are main ways to prevent abnormal events occurring on these equipments. Different from small equipment, large-scale complicated equipment always has numerous components and complex internal structure. FMEA has weak ability to represent the complex relation between faults of different component. Also, FTA modeling is time intensive and unreliable when equipment structure becomes complicated. According to these problems, this paper proposed a fault root cause tracing method of large-scale complicated equipment based on fault graph (FG). FG is a special kind of fault-oriented directed graph expanded from fault tree, which takes advantage of graph rather than tree to describe complex relation between fault modes of components, and add logic “AND” and “OR” connectives. FG is a useful tool to model the complex structure and fault affecting relation between components of large-scale complicated equipment in process industry, and can be used to trace fault root causes effectively in system failure of equipment. In this method, FMEA is used firstly to extract fault modes and fault affecting relation between components of equipment. The fault modes and their affecting relation are stored in polychromatic matrix. Then the polychromatic matrix of fault modes and their affecting relation is converted into FG automatically by algorithm with several rules. The FG can represent complex fault affecting relation between components of the equipment conveniently. The reachability from the failure nodes of FG is then calculated to obtain those possible fault transfer reachable components. The fault transfer pathways from root causes to failure component is searched based on graph-theoretic methods. An example of FG modeling and fault analysis of turbine which has complex internal structure and is widely used in process industry is introduced. The example proved that the proposed method is effective for fault root cause tracing of large-scale complicated equipment.

This paper reports on a new type of through-silicon via (TSV) defect, silicon fin defect, which was found after TSV deep-reactive-ion-etching (DRIE) process for TSV integration with front-end-of-line (FEOL) devices. One possible root cause for this defect is that the bulk micro defect (BMD) in silicon substrate serves as a micro-mask during etching and results in silicon fin defects at TSV bottom. These defects have to be eliminated as they are killer TSV defects for several reasons: (1) could serve as a weak point for isolation liner deposition; (2) could be a weak point for barrier/seed layer deposition; and (3) may cause mechanical failures during TSV backside reveal. Previously, silicon fin defects were removed by switching to a non-BMD silicon substrate for interposer application. However, for TSV integration with FEOL devices, the BMD layer serves as an intrinsic gettering layer for devices, therefore, it cannot be removed from the silicon substrate, which makes it challenging to get rid of silicon fin defects. In order to establish a non-destructive in-line detection method of the fin defects, scanning electron microscope (SEM) automatic process inspection (API) was set up to image the fin defects at the bottom of the trench. A special working point with high depth of focus (DoF) and contrast was created to obtain good top-down SEM imaging of the defects at the bottom of this high-aspect-ratio (HAR) structure. Three types of silicon substrates (A, B, and C) were used for this study to investigate the potential root cause. SEM API results show defect rates of 20%, 3.3% and 0% for substrates A, B, and C, respectively. This is in good agreement with both BMD simulation results and benchmarking data in which substrates A, B, and C had normalized BMD densities of 11.7, 5.74, and 1 cm-3, respectively, with a comparable BMD size of 80~90 nm and a denuded zone (DNZ) depth of 10~15 μm. The correlation between BMD density in a silicon substrate and silicon fin defect rate indicates that BMD is a key root cause for silicon fin defects. To eliminate silicon fin defects, an optimized DRIE process has been developed. On the same type of substrate, the DRIE process with a typical voltage bias results in a defect rate of 6.7%, while no silicon fin defect was detected out of 200 TSVs with a polynomial bias ramp to relatively higher final voltage bias during the last 15 μm etch. The hypothesis is that higher voltage bias is able to sputter away BMD and shows potential to get rid of the silicon fin defects at the TSV bottom. In summary, a capable inspection method, a preferred silicon substrate with BMD spec range, and a promising way for DRIE process optimization to eliminate the silicon fin defect at the TSV bottom have been identified and developed in this work. Detailed results and analysis, particularly the fin defect images, statistical inspection results, BMD benchmarking data, simulation results, and TSV profile with optimized process will be discussed in the paper.

Defect localization on a digital block is challenging, since modern gate densities makes in-circuit micro-probing to do voltage mapping almost impossible. Additionally, large top metal layer areas often preclude the use of top-side analysis to validate a fault isolation result. However, with in-depth circuit analysis, the correlation between electrical failure mode and fault isolation result can be established, which facilitates identification of the most probable defective node within the faulty block. Further fault localization techniques, such as curve trace micro-probing and OBIRCH analysis, perform a vital role in identifying the defect location. A case study is presented to demonstrate that the failure mechanism can be successfully determined using these techniques.

Modern large frame F, G, & J class gas turbine flow path component design requires the complex integration of multiple design disciplines that traditionally reside with distinct specialists. A traditional design system for an actively cooled gas turbine blade includes aerodynamicists, heat transfer engineers, structural engineers and a failure or lifetime prediction engineers passing information through a manual process with a small number of iterations between the disciplines. Design or manufacturing engineers can also be involved ensuring manufacturability and policing best practices in a predominantly deterministic design system. Over the past few decades robust design or probabilistic design philosophies along with cluster computing advancements have accelerated the release of commercial software that allows for the automation of multiple analytical evaluations at off design points. These software codes allow for process automation of several independent codes executed multiple times at various conditions for automated design of experiment (DOE), and reliability analysis using Monte Carlo or other advanced approximate probabilistic methods across the entire design system. In this paper, the authors are presenting a novel approach of using a commercially available process integration tool to fully integrate a series of other commercially available tools for a root cause failure analysis of a F class turbine blade rather than a new make design. The analysis incorporated a computational fluid dynamics model (CFD) to define inlet temperatures and pressure profiles, a fully conjugate thermal analysis interacting with a finite element (FEA) solver linked to a proprietary creep lifetime prediction model. A DOE was executed to define the meaningful parameters and help rule out potential causes of failure such as loss of coating or compromised cooling system as a contributing factor of the failure which greatly reduced the amount of time and money needed for the investigation. A probabilistic failure analysis was then executed and surrogate models created for quick probabilistic assessment for different operating conditions. This allowed for validation against fleet history to explain the single engine failure not previously observed. Setting up the non-deterministic models initially allowed for rapid redesign in less than 1 month time with confidence that the true root cause was identified and mitigated. It further allowed for feedback and calibrations to the traditional design system methodology.

In this paper we show an efficient workflow that combines Magnetic Field Imaging (MFI) and Dual Beam Plasma Focused Ion Beam (DB-PFIB) for fast and efficient Fault Isolation and root cause analysis in 2.5/3D devices. The work proves MFI is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) triple stacked devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a DB-PFIB system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. With a DB-PFIB, the fault is exposed and analyzed without any sample prep artifacts seen in mechanical polishing or laser preparation techniques and done in a considerably shorter amount of time than that required when using a traditional Gallium Focused Ion Beam (FIB).

A dual beam FIB (Focused Ion Beam) system which provides the ion beam (i-beam) and electron beam (e-beam) function are widely used in semiconductor manufacture for construction analysis and failure cause identification. Although FIB is useful for defect or structure inspection, sometimes, it is still difficult to diagnose the root cause via FIB e-beam image due to resolution limitation especially in products using nano meter scale processes. This restriction will deeply impact the FA analysts for worst site or real failure site judgment. The insufficient e-beam resolution can be overcome by advanced TEM (Transmission Electron Microscope) technology, but how can we know if this suspected failure site is a real killer or not when looking at the insufficient e-beam images inside a dual beam tool? Therefore, a novel technique of device measurement by using C-AFM (Conductive Atomic Force Microscope) or Nano-Probing system after cross-sectional (X-S) FIB inspection has been developed based on this requirement. This newly developed technology provides a good chance for the FA analysts to have a device characteristic study before TEM sample preparation. If there is any device characteristic shift by electrical measurement, the following TEM image should show a solid process abnormality with very high confidence. Oppositely, if no device characteristic shift can be measured, FIB milling is suggested to find the real fail site instead of trying TEM inspection directly.

Failure analysis plays an important role in yield improvement during semiconductor process development and device manufacturing. It includes two main steps. The first step is to find the defect and the second step is to identify the root cause. In the past, failure analysis mainly focused on the first step, namely how to find the defect for a failure; because in the previous generations of technology, once the defect was found, its root cause was relatively easy to be understood. As the current advanced semiconductor technology has become tremendously complicated, especially 3D devices, like FinFET, a defect found by failure analysis can be substantially transformed from its original defect by subsequent processes and can be totally different from its origin in size and shape. Thus, sometimes, the second step, identifying the root cause for a defect becomes more challenging and takes more time than the first step. With combination of failure analysis and inline inspection, it enables us to establish the relationship between the failure analysis defect and an in-line defect. This can link the defect for a device functional failure to its source layer and process step more quickly, leading to fast root cause identification. In this paper, the methodology was validated by fast identification of the root causes for three case studies in the latest FinFET technology.

Embed SRAM IDDOFF fail root cause identification by combination of device analysis and localized circuit analysis