Application of Graphical Hardware Programming in Non-Computer Major

This study presents a new method on 3D visualization in reservoir modeling system by using the computation power of modern programmable Graphics hardware (GPU). The proposed scheme is devised to achieve parallel processing of massive reservoir logging data. By taking advantage of the GPU's parallel processing capability, moreover, the performance of our scheme is discussed in comparison with that of the implementation entirely running on CPU. Experimental results clearly show that the proposed parallel processing can remarkably accelerate the data clustering task. Especially, although data-transferring from GPU to CPU is generally costly, acceleration by GPU is significant to save the total execution time of data-clustering and also significantly alleviates the computing load on CPU.

RETRACTED: Analysis of psychological education factors based on computer software and hardware collaboration and data mining

Cluster rendering is very necessary in today’s 3D animation rendering and HD post video production. From the initial processing of a single still image to the current rendering of video and 3D scene, from the original rendering process requires a lot of manual interaction to the current computer automatic recognition and rendering. Due to the support of programmable graphics hardware, many rendering technologies can render video or 3D scene in real time and become animation after improvement and acceleration. One of the biggest problems in stylized line drawing of 3D models is the calculation of visibility. In the current algorithm for calculating line visibility with complex models, either the interactive rendering speed is too slow or the rendered animation is incoherent. An algorithm for fast, high-quality calculation of line visibility under the GPU, which utilizes advanced programmable graphics pipeline technology that supports line visibility and a wide range of stylization options. This paper studies the energy consumption of rendering clusters in the field of 3D animation rendering, adopts the task volume prediction model based on neural network, and combines the historical data statistics of rendering system task volume, and proposes a multi-step prediction-based rendering cluster automatic on-off control algorithm and energy-saving control architecture. And the effectiveness of the energy-saving control method is verified by actual data.

Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.

A lot of research work has been carried out on the smart city and its applications in last two decades. Smart transportation is an application of smart city and also an important factor in building smart cities. Due to the complexity in passenger's traffic in big cities, a smart transportation system is needed to resolve the issue. This paper examines the concept of a vision-based transportation system to resolve the complexities in passenger's traffic and improving the productivity of existing transportation system. The vision-based transportation systems are expected to have positive mobility effects and be able to subsidize to the green environment by improving air quality and energy conservation for planning and developing a smart city. Thus, vision-based transportation is possibly an important approach for supporting and improving the transportation system. Vision-based transportation is a set of technologies applied to transportation infrastructure and vehicles to improve their performance. More specifically, vision-based transportation involves the application of established communications, controls, electronics, computer hardware, and software technologies in the transportation system. The paper examines in detail a broad range of vision-based transportation technologies and the expected benefits. These benefits include improved transportation system, travel time, throughput, cost savings, and most importantly safety and security. The paper considers a set of barriers that are required for the improvement of autonomous vehicles.

Within the strongly regulated avionic engineering field, conventional graphical desktop hardware and software application programming interface (API) cannot be used because they do not conform to the avionic certification standards. We observe the need for better avionic graphical hardware, but system engineers lack system design tools related to graphical hardware. The endorsement of an optimal hardware architecture by estimating the performance of a graphical software, when a stable rendering engine does not yet exist, represents a major challenge. As proven by previous hardware emulation tools, there is also a potential for development cost reduction, by enabling developers to have a first estimation of the performance of its graphical engine early in the development cycle. In this paper, we propose to replace expensive development platforms by predictive software running on a desktop computer. More precisely, we present a system design tool that helps predict the rendering performance of graphical hardware based on the OpenGL Safety Critical API. First, we create nonparametric models of the underlying hardware, with machine learning, by analyzing the instantaneous frames per second (FPS) of the rendering of a synthetic 3D scene and by drawing multiple times with various characteristics that are typically found in synthetic vision applications. The number of characteristic combinations used during this supervised training phase is a subset of all possible combinations, but performance predictions can be arbitrarily extrapolated. To validate our models, we render an industrial scene with characteristic combinations not used during the training phase and we compare the predictions to those real values. We find a median prediction error of less than 4 FPS.

Advances in computer hardware have made significant impact in the remote sensing field. Advanced graphical workstations allow researchers to display processed data in various formats in real time for better understanding of data. The visualization process also greatly facilitates validation of theoretical models for remote sensing and their applications to radar system studies. For example, synthesized radar images can be generated by computer programs instead of using actual hardware. Owing to the complexity of terrain scattering models, past efforts in radar image simulation have often been based on available measurement data with semi-empirical statistical models. In the present work, a graphical simulation program for radar imagery is developed using a first-principle based scattering model named EMSARS (Electromagnetic Model of Scattering Applied to Remote Sensing). It incorporates both volume scattering and surface scattering effects. The simulation program uses as input the complete GIS (Geographic Information System) database, including terrain features and elevation maps as well as detailed ground truth information, and incorporates the effects of shadowing, layover, and penetration loss. A graphical user interface is built for dynamically altering terrain conditions. The use of the simulation tool for evaluating and predicting radar system performance is demonstrated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The applications of embedded systems are widespread not only in consumer products and industrial machines but also for ubiquitous or sensor networking. However, the number of embedded system engineers is small and a few universities in Japan offer education pertaining to embedded systems. Embedded system engineers should acquire both the hardware (HW) and software (SW) technologies. We propose an educational method using student experiments to train embedded SW engineers who understand HW technologies. The experiments are related to developing SW, designing FPGA devices and learning HW/SW co-design. By conducting these experiments, students learn system modeling, HW/SW trade-off and development of SW and HW modules. We developed a JPEG encoder experiment using HW/SW co-design for evaluation.

The partitioning between hardware (HW) components and software (SW) components plays a major role in the codesign process of Embedded Systems (ES). Defining a good partitioning at early stage of the design allows improving the system performance, meeting the time to market and optimizing several other metrics. The majority of works made a focus on execution time and hardware area metrics while dealing with the hardware software partitioning (HSP) problem, and in some cases the power consumption metric was also taking in consideration. In this paper, we propose a novel approach in order to optimize simultaneously several metrics while respecting a constraint on global hardware area. The proposed approach is implemented using 0–1 Knapsack Problem (KP) algorithm. Experimental results show that the proposed algorithm is very fast and gives more reliable solutions comparing to Genetic Algorithm (GA) and Simulated Annealing (SA) algorithm.

This paper describes the pedagogy of how the 7-week course on computer fundamentals is introduced and taught to a class of 700 first year undergraduate students from the schools of business and computing. The computer fundamentals course itself covers theoretical topics such as the hardware and software of computers, information systems and programming basics as well as practical topics such as using office productivity software and basic programming. This course was conducted using a hybrid learning approach in which video lectures were used in conjunction with face-to-face practical work. The design, method, experience and recommendations from conducting this course will be presented. Feedback from 261 students regarding how the teaching had benefited their learning on average is 61% positive, 11% negative and the remaining were neutral.

A novel framework shows the potential of FPGA-based systems for increasing fault-tolerance and flexibility by placing functionality onto free hardware (HW) or software (SW) resources at runtime. Based on field-programmable gate arrays (FPGAs) in combination with CPUs, tasks implemented in HW or SW will migrate between computational nodes in a network. Moreover, if not enough HW/SW resources are available, the migration of functionality from HW to SW or vice versa is provided. By integrating this resource management, also called online HW/SW partitioning, in a distributed operating system for networked systems, a substantial step towards self-adaptive systems has been done. Besides a short motivation for this project and the presentation of related work, this paper gives an idea about a novel approach and a powerful experimental setup.

Hardware-aware neural architecture search for stochastic computing-based neural networks on tiny devices

As an important component of urban landscape elements, garden plants have the role of improving urban ecological environment and forming landscape effects. Digital landscape is a high-simulation model of the system combined with computer hardware and software systems, which allow analysis of the application of computer simulation in the analysis of the value of urban landscape design. In this paper, we propose a “Task-Crowd-Process-Evaluation” computer simulation analysis framework to support management decision, which can form 2D or 3D spatial data, realize real-time and statistical analysis, make use of the multidimensional, efficient, and humanized human living environment, and make the environment landscape planning more reasonable and practical. The simulation shows that the effective use of urban vegetation can not only beautify the urban landscape, but also play the function of rainwater utilization.

Simulation Validation and ManagementJohn D. IligenIligen Simulation Technologies, Inc.250 Storke RoadSuite 10Goleta, California 93117jillgen@illgen.comABSTRACTThe past several years have seen many technological advances in both computer hardware and software. Computer hardwareis becoming very complex. Computer hardware and software have virtually taken over every aspect of our lives, both in thehome and in the workplace. The government is looking at computer modeling and simulation (MIS) as a way of predictingcomplex system behavior without having to construct expensive prototypes or conduct extensive field tests. Decision makersare demanding that the use of M/S be made an integral part of any major system acquisition.As the use of computer software increases, there has been a concomitant call for uniform policies and procedures that willprovide assurance as to their credibility. Thus, the Verification and Validation (V&V) of M/S has also taken on new mean-ing. While software V&V has long been recognized as the means to credibility, only recently has it become seen as a neces-sary requirement. Standard definitions have been promulgated by the Department of Defense (DoD Directive 5000.59).Committees, working groups, and conferences are devoting much of their time to the subject. Unfortunately, because ofthese various disparate activities, confusion abounds because there is NO standard methodology for V&V. Enter the Distrib-uted Interactive Simulation (DIS), which is adding another layer of complexity, and this confusion turns into chaos.iligen Simulation Technologies, Inc. (1511) has been working IV& -rograms for the past six years. As a result, they haveevolved a methodology that has been adopted and successfully implemented by a number of different IV&V programs. Thismethodology employs a unique use of Computer Assisted Software Engineering (CASE) tools to reverse engineer source codeand produce analytical outputs (flow charts and tables) that aid the engineer/analyst in the V&V process. We have found thatthe use of CASE tools saves time, which equates to improvements in both schedule and cost. This paper will describe theISTI-developed methodology and how CASE tools are used in its support. Case studies will be discussed.1. INTRODUCTIONAs Figure 1 illustrates, technology has changed a lot in the last ten years. So has the way the DoD is doing business. At thattime, most M/S were executed on mainframe computers. At that time microprocessors, as we know them today, were justbecoming known. The IBM-compatible XT was the hot item, but it could not support computationally intensive programssuch as sophisticated MIS. In those time, MIS was not well understood. They were considered a play toy of the engi-neer/scientist. Since mainframes weren't known for their user-friendly ways, decision makers and higher-level executivesweren't known to waste their time trying to understand them.

System emulation technology enables users to rapidly prototype HDL-based designs on programmable hardware before committing their designs to production. In this paper, we show that this methodology is particularly viable for at-speed verification of communications designs. We show how complimentary tools can be used to generate HDL code for a digital wireless communications system. Then we consider how this design can be implemented and evaluated using a rapid prototyping methodology. Synthesis produces a gate-level specification for implementation in FPGAs which are combined with other components in the Aptix rapid prototyping environment. Issues discussed include: software tool flows, prototype hardware assembly, system performance and debugging.