Applying an optimized switching strategy to a high gain boost converter for input current ripple cancellation

This paper proposes an optimal methodology based on the Differential Evolution algorithm for obtaining the set of duty cycles of a recently proposed power electronics converter with input current ripple cancelation capability. The converter understudy was recently introduced to the state-of-the-art as the interleaved connection of two unequal converters to achieve low input current ripple. A latter contribution proposed a so-called proportional strategy. The strategy can be described as the equations to relate the duty cycles of the unequal power stages. This article proposes a third switching strategy that provides a lower input current ripple than the proportional strategy. This is made by considering duty cycles independently of each other instead of proportionally. The proposed method uses the Differential Evolution algorithm to determine the optimal switching pattern that allows high quality at the input current side, given the reactive components, the switching frequency, and power levels. The mathematical model of the converter is analyzed, and thus, the decision variables and the optimization problem are well set. The proposed methodology is validated through numerical experimentation, which shows that the proposed method achieves lower input current ripples than the proportional strategy.

This paper analyzes a coupled inductor based $LL$ – $LC$ network as a building block to achieve input or output current ripple cancellation in power converters. The proposed current ripple cancellation technique works on the principle of inductance matching. It also provides reduced current stress on the switching devices of the converter compared with the other current ripple cancellation networks discussed in the literature. The current ripple cancellation technique is verified in achieving input and output current ripple minimization in different converters. The effect of inductance mismatch, inductor and capacitor tolerances, and circuit parasitic is also studied. Some of the published research works are demonstrated to be a special case of the proposed idea. The effectiveness of the proposed method is validated by demonstrating the zero-ripple input current using a 31 V dc to 60 V dc, 240 W boost converter prototype and a 31 V dc to 115 V (rms) ac, 320 W current-fed-switched inverter prototype, and the zero-ripple output current using a 62 V to 42 V dc, 450 W buck converter prototype.

Analysis and minimization of input current and voltage ripples of five-phase PWM inverters are presented in this paper. The analytical expressions for the RMS value of input current and voltage ripples as a function of the PWM reference signal are derived. Different to three-phase PWM inverters, it is shown that pure sinusoidal is the optimum reference signal that produces minimum input voltage ripple. Input current ripple does not depend on the employed reference signal so the ripple canpsilat be minimized by changing reference signal. Simulation and experimental results verify the analysis.

This paper presents an analysis of input and output ripples of PWM AC choppers. Expressions of input and output current and voltage ripples of single-phase PWM AC choppers are first derived. The derived expressions are then extended to three-phase PWM AC choppers. As input current and output voltage ripples specification alone cannot be used to determine the unique values of inductance and capacitance of the LC filters, an additional criterion based on the minimum reactive power is proposed. Experimental results are included in this paper to show the validity of the proposed analysis method.

Input ripple analysis of five-phase pulse width modulated (PWM) inverters is presented. The analytical expressions for the rms value of the input current and voltage ripples as a function of the PWM reference signal are derived. Similar to three-phase PWM inverters, the input current ripple does not depend on the employed reference signal, so the ripple cannot be minimised by changing the shape of reference signal. On the other hand, different from three-phase PWM inverters, it is shown that a pure sinusoidal signal is the optimum reference signal that produces a minimum input voltage ripple in five-phase PWM inverters. Input voltage ripples under several modulation techniques are compared. Experimental results are included to verify the proposed analysis method.

This paper proposes a multi-phase charge pump for high voltage output applications. The simple topology combines a voltage doubler with an inverting charge pump that are paralleled to provide an output voltage that is three times the input voltage. The operation of the proposed topology and the effects of multi-phasing and varying duty cycle on the input current ripple, output voltage and current ripple as well as total harmonic distortion are analyzed using LTSpice simulation. Benefits and issues from the proposed configuration will also be discussed.

The Weinberg converter is a suitable choice for the battery discharge regulator of a geostationary satellite due to its high efficiency, continuous input and output current, and soft switching of switches and diodes. Nevertheless, this converter has high output current ripple during the commutation period of its output diodes. Therefore, the output RMS current and output voltage ripple are high, which may directly affect the lifetime and total capacitance of bus capacitors and hence, the lifetime and volume of the geostationary satellite. Thus, reducing the output current ripple is important to the design of the geostationary satellite. An improved Weinberg converter with an additional inductor and capacitor is proposed in this paper to reduce the output current and voltage ripple. It features soft switching of all switches, no reverse recovery problems of the diodes, and reduced magnetizing offset current in the coupled inductor. The proposed converter is verified with experimental results from a 750W, 100kHz, 36-50Vdc prototype.

A high gain bidirectional DC-DC converter is described in this paper. This converter consist of a buck-boost topology which has continuous input current followed by a high gain switched-capacitor based boost converter [11]. The modified converter has six switches with their body diodes. The operation of switches is in such a way that three switches requires gate pulse from each side of operation. The current ripple cancellation at low voltage side and low switches voltage stress are the main feature of this modified converter. Compared to other buck-boost converters, the converter's voltage gain is more in boosting mode. The simulation study is carried out and presented for validation of the modified converter effectiveness.

This paper presents a new soft switching (SS) multiphase interleaved boost converter (MIBC) consisting of three boost converters (BCs) that operate rapidly and efficiently to charge a lithium-ion battery for photovoltaic (PV) power system applications. This suggested converter can operate both active power switches at zero current switching (ZCS), and when switched off, it works at zero voltage switching (ZVS), which reduces switching losses and increases switching efficiency (SF). An interleaving structure is employed to decrease the conduction losses and reduce the input current ripple (ICR) and output voltage ripple (OVR) to increase the power rating. The suggested converter regulates the input and output power by modulating the phase shift in the pulse width modulation (PWM) technique using the maximum power point tracking (MPPT) algorithm via two closed feedback loops, one for a slower external loop and the other for a faster PWM control internal loop, similar to current mode control. The suggested converter has high voltage (HV) gain due to the coupled inductors (CIs), which act as a transformer. This magnetic design structure in both the steady-state and transient states also decreases the size and enhances the converter’s performance. Finally, the suggested converter was experimentally verified on a 285W prototype, and the maximum efficiency was found to be 98%, based on modeling and experimental data.

This paper presents an extended coupled inductor quasi-Z-source inverter (ECL-QZSI), which has advantages like input current ripple suppression and high gain ability. Adding third coupled winding series with the input inductor causes to reduce high-frequency input current ripple. Among the impedance source converters in the same condition to have equal current ripple, the amount of inductor will be decreased significantly compared to the absence of third series winding. Unlike trans-Z-source inverter, in proposed topology input current is continuous which eliminates protector energy source filter and voltage gain is boosted by reducing turns number of primary winding transformer which decreased costs and volume of the transformer. In comparison with improved $\Gamma\text{ZSI}$ , proposed converter provides high voltage gain ability. Therefore, ECL-QZSI uses lower duty cycle and consequently higher modulation ratio with reduced elements stress and enhanced quality of output waveforms. All the aforementioned ECL-QZSI features are validated through simulation results in PSIM software and theoretical equations that are given in the following to confirm function of the suggested structure.

In this paper, a novel nonisolated interleaved high step-up DC-DC converter is proposed based on the coupled inductor and voltage multiplier cell (VMC) methods. Due to the interleaved structure, its input current ripple is low. The low input current ripple and also high power efficiency make the proposed converter suitable for renewable energy applications like photovoltaic (PV) and fuel cell (FC) power generation systems. The windings of the coupled inductors are combined with VMCs to further increase the output voltage with a low power switch’s duty cycle. This combination also leads to obtaining a flexible voltage gain that can be adjusted by coupled inductors’ turns ratio and power switches’ duty cycle. The voltage peaks over semiconductors are much lower than the output voltage. Therefore, low-rated semiconductors can be used for the implementation of the proposed converter, which can reduce the cost and volume. Generally, high voltage gain, low voltage, current stress of power switches, low input current ripple, high efficiency, common ground between the input and output ports, and a low number of elements are the main benefits of the suggested structure. The operation principle, steady-state analysis, and comparison with other converters are presented to show the advantages of the suggested converter. Also, a prototype is built, and the experimental results are presented to prove the theoretical analysis. This prototype is implemented with 200 W rated power, 25 V∼400 V voltage conversion, and 50 kHz switching frequency. Additionally, the efficiency is measured at 95.3% at the rated power.

This paper presents the analysin ,design and implementation of a high voltage ratio topology of DC-DC converter. The DC-DC converter has high voltage ratio with reduced input current, output voltage and output current ripple, and also reduces the voltage and current rating of power electronics components and compared with conventional boost converter. The voltage stress on the switches are reduced in this topology. Analysis, design and converter operating waveforms in the continuous conduction mode are provided along with design guidelines. The converter has been designed for rated power of 50W, input voltage of 24V, output voltage of 72V and switching frequency of 25 kHz. The floating output interleaved input high voltage gain converter is compared with conventional boost converter, hardware and simulation results are verified.

This paper presents a multi-cell single-phase high power factor boost rectifier in interleave connection, operating in critical conduction mode, employing a soft-switching technique, and controlled by field programmable gate array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for all interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a implemented prototype with two and with four interleaved cells, 400 V nominal output voltage and 220 Vrms nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device

This paper proposes an interleaved high step-up DC-DC converter with the coupled inductor (CI) and built-in transformer (BIT) for renewable energy applications. Two double-winding (2W) CIs and one triple-winding (3W) BIT are integrated with the switched-capacitor (SC) voltage multiplier cells (VMCs) to achieve high-voltage gains without extreme duty cycles. The CIs and BIT turns-ratios provide two other degrees of freedom—in addition to the duty cycle—to adjust the voltage gain that leads to increased design flexibility. The diodes turn off naturally under the zero-current switching (ZCS) conditions because their current falling rates are controlled by the leakage inductances of the CIs and BIT; therefore, the diodes’ reverse-recovery problems are alleviated. Moreover, employing passive diode-capacitor clamp circuits, the voltage stresses of the switches are limited to a low value far less than the output voltage. Additionally, the leakage inductances energies are recycled and transferred to the output to further extend the voltage gain. Furthermore, due to the interleaved structure, the input current ripple and current stresses of the components are reduced. The proposed converter is analyzed in detail and then compared with similar converters that employed CIs and/or BIT along with passive/active clamp circuits for the MOSFETs. Finally, to verify the feasibility of the proposed converter, the experimental results of a 200 W prototype with output voltage of 400 V and voltage gain of 25 are presented.

This paper proposes novel bidirectional DC-DC converter that has the advantages of high voltage gain, low conduction losses and low input current ripple. Two paralleled current-fed full bridges are located in the low voltage side (LVS), sharing one voltage-fed full bride in high voltage side (HVS). A quadruple phase-shift control strategy is proposed to reduce input current ripple and conduction loss. The phase shift between the full-bridges of LVS is employed to greatly reduce current ripple and the auxiliary inductors are used to help the lag bridge extend the zero-voltage-switch (ZVS) range. Finally, an 800W simulation prototype is built to verify the proposed converter, the accordance between the analysis and simulation results testify the advantages.