Architecting Optically Controlled Phase Change Memory

This research aims to design a new phase-change RAM (PRAM)-based main memory structure, supporting the advantages of PRAM while providing performance similar to that of conventional DRAM main memory. To replace conventional DRAMs with non-volatile PRAMs as the main memory components, comparable memory access latency, overall cost, power dissipation, and memory cell endurance should be supported. For these goals, we propose a new main memory system consisting of a DRAM converter and an array of single-level cell (SLC)/multi-level cell (MLC) PRAMs. The DRAM converter consists of an aggressive fetching superblock buffer to assure better use of spatial locality and a selective filtering buffer for better use of temporal locality. The array of the SLC/MLC hybrid PRAM structure includes a combination of SLC and MLC PRAMs to enhance the lifetime of the MLC PRAM main memory and hide asymmetric read/write access latency. The proposed structure is evaluated by a trace-driven simulator using SPEC CPU 2006 and SPLASH-2 traces. Experimental results show that the proposed DRAM converter can reduce the miss rate by ∼37% and write count by ∼55% in comparison with the uniform buffer case. Also, the SLC/MLC PRAM with DRAM converter shows performance in terms of access latency and power consumption close to that of the conventional memory architecture. Thus, our proposed memory architecture can be used to replace the current DRAM-based main memory system.

Using nonvolatile memories in memory hierarchy has been investigated to reduce its energy consumption because nonvolatile memories consume zero leakage power in memory cells. One of the difficulties is, however, that the endurance of most nonvolatile memory technologies is much shorter than the conventional SRAM and DRAM technology. This has limited its usage to only the low levels of a memory hierarchy, e.g., disks, that is far from the CPU.

Green cloud is an emerging new technology in the computing world in which memory is a critical component. Phase-change memory (PCM) is one of the most promising alternative techniques to the dynamic random access memory (DRAM) that faces the scalability wall. Recent research has been focusing on the multi-level cell (MLC) of PCM. By precisely arranging multiple levels of resistance inside a PCM cell, more than one bit of data can be stored in one single PCM cell. However, the MLC PCM suffers from the degradation of performance compared to the single-level cell (SLC) PCM, due to the longer memory access time. In this paper, we present a genetic-based optimization algorithm for chip multiprocessor (CMP) equipped with PCM memory in green clouds. The proposed genetic-based algorithm not only schedules and assigns tasks to cores in the CMP system, but also provides a PCM MLC configuration that balances the PCM memory performance as well as the efficiency. The experimental results show that our genetic-based algorithm can significantly reduce the maximum memory usage by 76.8 percent comparing with the uniform SLC configuration, and improve the efficiency of memory usage by 127 percent comparing with the uniform 4 bits/cell MLC configuration. Moreover, the performance of the system is also improved by 24.5 percent comparing with the uniform 4 bits/cell MLC configuration in terms of total execution time.

Phase change memory (PCM) is non-volatile memory that is byte-addressable. It is two to four times denser than DRAM, orders of magnitude better than NAND Flash memory in read latency, and 10 times better than NAND Flash memory in write endurance. However, it still limits the number of write operations to at most 106 times per PCM cell. To extend its lifetime, it is necessary to evenly distribute write operations over all the memory cells. Up to now, the B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree index structure has been used to quickly locate a search key in a relational database management system (RDBMS). All the record keys in each node are sorted and packed upon insertion in, and deletion from, the B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree. In addition, a counter keeps track of the number of valid keys in the B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree. Consequently, a B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree algorithm results in a large number of write operations, which deteriorates the endurance of PCM. This restricts the usage of PCM on a database server and deteriorates performance of database servers. In this paper, we propose a novel PCM-aware B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree index structure, called PB <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree, to provide wear-leveling in PCM. According to our experiment results, PB <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree is much faster than the existing B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree algorithms for PCM and NAND Flash memory with versatile workloads. More importantly, our scheme also greatly reduces the number of write operations compared to other B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree algorithms. All of these results suggest that PB <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree is the B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -Tree algorithm best fitted to PCM.

Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where the reliability depends on the data pattern, a tri-level-cell (3LC) PCM has significantly higher performance and lifetime than a four-level-cell (4LC) PCM. However, a storage density is limited by binary-to-ternary data mapping. This paper introduces error-vulnerable pattern-aware binary-to-ternary data mapping utilizing 3LC PCM without an error-correction code (ECC) to enhance the storage density. To mitigate the storage density loss caused by the 3LC PCM, a two-way encoding is applied. The performance degradation is minimized through parallel encoding. The experimental results demonstrate that the proposed method improves the storage density by 17.9%. Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.

Conventional DRAM and flash memory are reaching their scaling limits thus motivating research in various emerging memory technologies as a potential replacement. Among these, phase change memory (PCM) has received considerable attention owing to its high scalability and multi-level cell (MLC) operation for high storage density. However, due to the resistance drift over time, the soft error rate in MLC PCM is high. Additionally, the iterative programming in MLC negatively impacts performance and cell endurance. The conventional methods to overcome the drift problem incur large overheads, impact memory lifetime and are inadequate in terms of acceptable soft error rate (SER). In this paper, we propose a new PCM memory architecture with heterogeneous PCM arrays to increase reliability, performance and lifetime. The basic storage unit in the proposed architecture consists of two single-level cells (SLCs) and one four-level cell (4LC). Using the reduced number of 4LCs compared to conventional homogeneous 4LC PCM arrays, the drift-induced error rate is considerably reduced. By alternating each cell operation between SLC and 4LC over time, the overall lifetime can also be significantly enhanced. The proposed architecture achieves up to 105 times lower soft error rate with considerably less ECC overhead. With simple ECC scheme, about 22% performance improvement is achieved and additionally, the overall lifetime is also enhanced by about 57%.

Emerging nonvolatile memory (NVM), such as spintransfer torque magnetic Memory (STT-RAM), phase-change memory (PCM), and resistive memory (ReRAM), are widely expected to become the next generation cache and main memory, in order to migrate the “power wall” and overcome the DRAM stability challenge. Previous effort has well explored NVM’s feature of ultra-low leakage and high density at various memory hierarchy. Furthermore, challenges such as asymmetric read/write, expensive write operation, and limited lifetime have also been tackled. However, the benefit from NVM’s nonvolatility has never been fully exploited. This paper points out the potential benefit by leveraging nonvolatility for architecture design. Two case studies are described. The first one is to leveraging multi-level cell (MLC) STT-RAM for ultra-low overhead local checkpointing. The second one is persistent memory design, which support persistency in NVM based main memory. Potential benefit and design challenge for those two cases are described. Future research topic around exploring NVM’s nonvolatility is also discussed.

Write bandwidth is an inherent performance bottleneck for Phase Change Memory (PCM) for two reasons. First, PCM cells have long programming time, and second, only a limited number of PCM cells can be programmed concurrently due to programming current and write circuit constraints,For each PCM write, the data bits of the write request are typically mapped to multiple cell groups and processed in parallel. We observed that an unbalanced distribution of modified data bits among cell groups significantly increases PCM write time and hurts effective write bandwidth. To address this issue, we first uncover the cyclical and cluster patterns for modified data bits. Next, we propose double XOR mapping (D-XOR) to distribute modified data bits among cell groups in a balanced way. D-XOR can reduce PCM write service time by 45% on average, which increases PCM write throughput by 1.8x. As error correction (redundant bits) is critical for PCM, we also consider the impact of redundancy information in mapping data and error correction bits to cell groups. Our techniques lead to a 51% average reduction in write service time for a PCM main memory with ECC, which increases IPC by 12%.

Write bandwidth is an inherent performance bottleneck for Phase Change Memory (PCM) for two reasons. First, PCM cells have long programming time, and second, only a limited number of PCM cells can be programmed concurrently due to programming current and write circuit constraints, For each PCM write, the data bits of the write request are typically mapped to multiple cell groups and processed in parallel. We observed that an unbalanced distribution of modified data bits among cell groups significantly increases PCM write time and hurts effective write bandwidth. To address this issue, we first uncover the cyclical and cluster patterns for modified data bits. Next, we propose double XOR mapping (D-XOR) to distribute modified data bits among cell groups in a balanced way. D-XOR can reduce PCM write service time by 45% on average, which increases PCM write throughput by 1.8x. As error correction (redundant bits) is critical for PCM, we also consider the impact of redundancy information in mapping data and error correction bits to cell groups. Our techniques lead to a 51% average reduction in write service time for a PCM main memory with ECC, which increases IPC by 12%.

Phase change memory (PCM) is a scalable, reliable, and robust technology for embedded and stand-alone memory device. PCM has also been extensively demonstrated for analog in-memory computing (IMC), which allows energy-efficient acceleration of AI workloads. High-temperature data retention requirements in PCM devices are met by Ge-rich GeSbTe (GST), which allows to satisfy consumer- and automotive-grade reliability specifications. However, Ge-rich GST suffers from set state drift, which affects the stability of the multilevel cell (MLC), hence the accuracy of IMC. This work presents: 1) a novel multilevel programming algorithm from weak reset state to prevent conductance instabilities; 2) a drift compensation scheme through a differential weight approach, validated on matrix-vector multiplication (MVM) after high-temperature annealing; and 3) a detailed study of the impact of PCM variability and weight quantization on hardware implementation of neural networks.

In the era of big data, the capability of computer systems must be enhanced to support 2.5 quintillion byte/day data delivery. Among the components of a computer system, main memory has a great impact on overall system performance. DRAM technology has been used over the past four decades to build main memories. However, the scalability of DRAM technology has faced serious challenges. To keep pace with the ever-increasing demand for larger main memory, some new alternative technologies have been introduced. Phase change memory (PCM) is considered as one of such technologies for substituting DRAM. PCM offers some noteworthy properties such as low static power consumption, nonvolatility, and capability of storing more than one bit per cell (multilevel cell, or MLC). However, the short lifetime and long access latency of PCM (specifically MLC PCM) require feasible and efficient solutions. In this article, based on the observation that applications access a significant number of read-friendly data blocks, we propose Express Read to prevent the MLC PCM read circuit to spend unnecessary time sensing the cells of a memory block. A read-friendly data block (RFDB) is composed of only “11” and “00” bit pairs, and thus upon sensing the most significant bit of a cell, the read operation can be early terminated to reduce the MLC read time and power consumption. Moreover, we increase the number of RFDBs using two simple techniques to better exploit the benefits of Express Read. Results obtained from full-system simulation near 6% performance improvement and 21% energy gain, on average, over the baseline system.

Phase change random access memory (PRAM) is one kind of nonvolatile memory, which is desirable to be used for DSP systems as main memory, as it consumes less power than DRAM and is much denser than DRAM. In this paper, we utilize a hybrid main memory composed of DRAM and PRAM, which leverages the low power consumption of PRAM while minimizing the performance and lifetime degradation caused by PRAM write. To make full use of different advantages of DRAM and PRAM, especially for the application-specific DSP systems, we reconsider the variable partitioning and instruction scheduling problems on the hybrid main memory. Different optimization objectives, for example power consumption, schedule length, and the number of writes on PRAM, are considered. At the same time, different kinds of hybrid architectures are analyzed. Graph models, ILP model, and algorithms are proposed for different settings. Experiments show that the proposed techniques reduce up to 49% power consumption and 88% the number of writes on PRAM on average.

A compiler assisted wear leveling for morphable PCM in embedded systems

Recently, Phase-Change Memory (PCM) has emerged as a promising memory and storage technology. By storing multiple bits in a PCM cell, Multi-Level-Cell (MLC) PCM further reduces the per-bit cost to improve its competitiveness. However, MLC PCM suffers from the high write latency and energy consumption caused by its complex write operations. Different from the existing works that attempt to improve the write latency and energy efficiency of the physical program&verify strategy for MLC PCM, we propose DTC, a drift-tolerant coding scheme, to apply fast write operation on MLC PCM without sacrificing the data accuracy. By exploiting the resistance drift and asymmetric write characteristics of PCM cells, the proposed DTC can significantly reduce the write latency and energy consumption of MLC PCM. Meanwhile, we propose a segmentation strategy to further improve the write performance with our coding scheme and an elimination methodology to avoid issuing unnecessary update operations. A series of analyses and experiments was conducted to evaluate the capability of the proposed scheme. It is encouraging that the proposed scheme can reduce 16.8-32.1% energy consumption and 20.1-32.6% write latency under the representative benchmarks, compared with the existing well-known schemes.

Due to its large leakage power and low density, the conventional SARM becomes less appealing to implement the large on-chip cache due to energy issue. Emerging non-volatile memory technologies, such as phase change memory (PCM) and spin-transfer torque RAM (STT-RAM), have advantages of low leakage power and high density, which makes them good candidates for on-chip cache. In particular, STT-RAM has longer endurance and shorter access latency over PCM. There are two kinds of STT-RAM so far: single-level cell (SLC) STT-RAM and multi-level cell (MLC) STT-RAM. Compared to the SLC STT-RAM, the MLC STT-RAM has higher density and lower leakage power, which makes it a even more promising candidate for future on-chip cache. However, MLC STT-RAM improves density at the cost of almost doubled write latency and energy compared to the SLC STT-RAM. These drawbacks degrade the system performance and diminish the energy benefits. To alleviate these problems, we propose a novel cache organization, companion write cache (CWC), which is a small fully associative SRAM cache, working with the main MLC STT-RAM cache in a master-and-servant way. The key function of CWC is to absorb the energy-consuming write updates from the MLC STT-RAM cache. The experimental results are promising that CWC can greatly reduce the write energy and dynamic energy, improve the performance and endurance of MLC STT-RAM cache compared to a baseline.