Architectural scheme for future embedded systems involving large number of processing cores

Abstract

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Embedded system design is the core for many time constraint application designs like avionics and railways. These systems employ multi core architecture for faster and time critical applications. Use of multi cores as the processing part is ever challenging due to the complexities involved in their designs, memory architecture, issues related to synchronization between the cores and problems like deadlock between the executing cores. Also as per the Moore's Law, number of cores on as ingle processing element increase exponentially becoming double after every 18 months. In the face of such fast increasing cores the time is not far when there will be 100 or 1000 of cores on a single chip. Then there will be bigger challenges of dealing with problems like heat dissipation, concurrency control and speedy communication between the cores, without compromising the performance and outcome of embedded systems employing these multiple cores. In this paper we have studied some of the pre existing protocols and technologies for handling concurrency in large number of multi core systems and have proposed a framework for concurrency control with a routing protocol for multi core system employing 64 cores. Then we have proposed to scale this system for higher number of cores leading to up to 100 cores and w ill study the performance on an embedded system.