Architectural support for performance tuning

The complexity of multi-level cache hierarchies simulation is much more complicated than that of single-level cache simulation, so that it is highly desirable to develop some efficient simulation methods for multi-level cache hierarchies performance analysis. A one pass multi-level unified cache hierarchies simulation method is developed based on stack model and inclusion properties. Recently, many processors utilized split instruction and data caches in the first cache level. A one pass multi-level hybrid cache simulation method is proposed for more generalized hierarchies. These two one pass simulation methods have been implemented. The simulation results show the effectiveness of these two one pass simulation methods. >

Collecting hardware event counts is essential to understanding program execution behavior. Contemporary systems offer few Performance Monitoring Counters (PMCs), thus only a small fraction of hardware events can be monitored simultaneously. We present new techniques to acquire counts for all available hardware events with high accuracy by multiplexing PMCs across multiple executions of the same program, then carefully reconciling and merging the multiple profiles into a single, coherent profile. We present a new metric for assessing the similarity of statistical distributions of event counts and show that our execution profiling approach performs significantly better than Hardware Event Multiplexing.

Introduction. This investigation explored 21st century stewardship of a late 20th century scientific oral history project through the lens of information practice. Oral history project stewardship and reuse are understudied. Literature review. Oral histories foreground human agency in the world. Often studied singly, many reflect an oral history project’s historiographic context. Stewardship documentation by multiple stakeholders accrues over time. The author developed an information practice analysis tool for systematic exploration of oral history stewardship documentation. Method. A case study approach and qualitative content analysis techniques guided investigation of documentation for an oral history project held at Science History Institute in Philadelphia. Textual data was collected for a purposive sample. Analysis and results. Multiple stakeholders’ documentation schema for the purposive sample were analysed in Excel and Word. Results coded five information work models for stakeholder information practices. Discussion. The information work models portrayed stakeholder information practices as mechanisms for stability in the stewardship of contextual assets, and mechanisms for transformation through staff knowledge, as situational assets. Conclusion. Information practice analysis of oral history stewardship in this case study systematised stakeholders’ and user perspectives on access. Implications for theory development lie in leveraging the stability and transformative agency of stewardship and reuse.

Impact of Information and Communications Technologies (ICTs) on sustainable transport development is indisputable. It can be tested through various methods. The identification and detailed analysis of specific types of ICT solutions, case studies approach or scenarios analysis are examples of perspectives for impact assessment that can lead to the proof that successful applications of ICT solutions entails optimised, more accessible, less resource consuming and less emission intensive transport. The impact of ICTs in travel induction and substitution and resulting decarbonisation effect is difficult to assess isolated from other social, economic and technologic drivers. Financial applicability reflects initial investment cost as well as operation maintenance costs. Organizational feasibility refers primarily to the necessary changes in organisation and conduct of operations created by introduction of ICTs. The social factor results from user and public acceptance or lack of it. User acceptance is combination of many sub factors of which most important are: D2D travel time, D2D travel costs, comfort and convenience, safety and security. The objective of the article is to present the applicability of ICT solutions in passenger transport from the perspective of transport users taking into consideration real case studies from different European background. These case studies were identified as a result of specific selection process in order to receive a complex and differentiated sample. The first element of the selection process was the identification of ICT solutions to be applied in case studies. The next element was the choice of regions corresponding to varied economic and geographic characteristics. In addition, cultural factors have a strong impact on the behaviour of users. The resulting multidimensional factor matrix allows for the selection of best fitting case studies, which have potential to cover most of the ICT applications. Five European settings are selected for in-depth research. Each case represents different geographic, social and economic area, which forms a good European sample across differentiated setups. Case studies are supported by user surveys. Surveys allow for direct answers regarding user attitudes towards proposed ICTs. Based on this approach findings could be reported. The main conclusion is that users in various regions with very different characteristics as to the wealth, GDP levels, geography, and cultural backgrounds represent surprisingly similar attitudes towards ICTs. Specific findings regarding different types of solutions and different type of users are presented in the article. The analysis of selected case studies shows also that they could offer solution to many of transport sector problems including key issues from transport policy agenda: environment, mobility or accessibility. The paper is based on the authors research conducted within COMPASS project (Optimised co-modal passenger transport for reducing carbon emissions, project co-funded by the European Commission within the Seventh Framework Programme).

Enabling timing analysis in the presence of caches has been pursued by the real-time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, caches heavily complicate timing analysis due to hard-to-predict access patterns, with few works dealing with time analyzability of multi-level cache hierarchies. For measurement-based timing analysis (MBTA) techniques — widely used in domains such as avionics, automotive, and rail — we propose several cache hierarchies amenable to MBTA. We focus on a probabilistic variant of MBTA (or MBPTA) that requires caches with time-randomized behavior whose execution time variability can be captured in the measurements taken during system's test runs. For this type of caches, we explore and propose different multi-level cache setups. From those, we choose a cost-effective cache hierarchy that we implement and integrate in a 4-core LEON3 RTL processor model and prototype in a FPGA. Our results show that our proposed setup implemented in RTL results in better (reduced) WCET estimates with similar implementation cost and no impact on average performance w.r.t. other MBPTA-amenable setups.

Multi-level caches are widely used to improve the memory access speed of multiprocessor systems. Deciding on a suitable set of cache memories for an application specific embedded system's memory hierarchy is a tedious problem, particularly in the case of MPSoCs. To accurately determine the number of hits and misses for all the configurations in the design space of an MPSoC, researchers extract the trace first using Instruction set simulators and then simulate using a software simulator. Such simulations take several hours to months. We propose a novel method based on specialized hardware which can quickly simulate the design space of cache configurations for a shared memory multiprocessor system on an FPGA, by analyzing the memory traces and calculating the cache hits and misses simultaneously. We demonstrate that our simulator can explore the cache design space of a quad-core system with private L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> caches and a shared L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> cache, over a range of standard benchmarks, taking as less as 0.106 seconds per million memory accesses, which is up to 456 times faster than the fastest known software based simulator. Since we emulate the program and analyze memory traces simultaneously, we eliminate the need to extract multiple memory access traces prior to simulation, which saves a significant amount of time during the design stage.

Registers within a processor, cache within, on, or outside the processor, and virtual memory on the disk drive builds memory hierarchy in modern computer systems. The principle of locality of reference makes this memory hierarchy work efficiently. In recent years, cache organizations and designs have witnessed several advances that have not only improved their performance such as hit rates, speed, latency, energy consumption, etc. but various new designs and organizations for chip multi-processors such as multilevel caches, Non-Uniform Cache Access (NUCA), hybrid caches, etc. have also emerged. This paper presents a study of current competing processors in terms of various factors determining performance and throughput of cache organization and design. To evaluate their performance and viability, it reviews recent cache trends that include hybrid cache memory, non-uniform cache architecture, energy efficient replacement algorithms, cache memory programming, software defined caches and emerging techniques for making cache reliable against soft errors. It discusses the pros and cons of emerging cache architectures and designs.

Network processors (NPs), a type of multicore, multithread system that exploits system-on-chip techniques, usually adopt a distributed, shared memory hierarchy to scale up network processing. Network applications running on NP often display distinct characteristics on memory subsystem compared with traditional processors with multilevel cache. As security, especially cryptography, has become indispensable in today's networks, we present a benchmark suite called NPCryptBench. It is the first benchmark specially designed to evaluate cryptographic performance on NPs, particularly that of processor and memory subsystem. By running NPCryptBench on Intel IXP network processors, we provide quantitative evidence that performance bottlenecks under such a highly parallel environment reside in memory hierarchy and prolonged access latency, instead of limited computing resources described in recent literature. To alleviate this memory-wall effect, we suggest several software optimizations, which averagely boost the benchmark throughput by 145% on Intel IXP2800. Our analysis and optimizations are also suitable for other NPs with similar architectures.

The IBM zEC12 has a robust, multi-level shared cache hierarchy that is designed to meet the needs of the enterprise class computing environment and represents a significant growth in system capacity and performance from its predecessor.

Handheld devices are becoming increasingly common in today's world. With every passing year, the diversity of applications (apps) being supported by mobile platforms is growing manyfold. In addition, Android, the most popular handheld OS in the market is releasing a new version every year, with a newer and richer set of APIs, enabling the next generation of feature-rich applications. To support these apps, hardware requirements of these devices are increasing rapidly. Mobile SoCs need a larger number of faster cores, better GPUs and above all, higher DRAM capacities to do justice to user experience. To augment capacity requirements, non-volatile memories (NVMs) have been proposed as a potential addition to LPDDR variants, which have been the mainstay of mobile SoCs. However, few tools exist to carry out architectural design space exploration of main memory hierarchies featuring NVMs for newer Android and app versions. In this paper, we present META, a trace based tool for facilitating the exploration of memory hierarchies in mobile devices. META uses an enhanced version of Android emulator for generating raw instruction traces. These traces are then fed into a cache hierarchy and memory simulation modules to carry out design space exploration for a wide variety of apps and memory technologies.

Despite the data-rich environment in which memory systems of modern computing platforms operate, many state-of-the-art architectural policies employed in memory system rely on static, human-designed heuristics that fail to adapt dynamically to workload and system behavior. In this article, we propose a fundamentally different design approach: using lightweight and practical machine learning (ML) methods to enable adaptive, data-driven control throughout the memory hierarchy. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">We present three ML-guided architectural policies: (1) Pythia, a reinforcement learning-based data prefetcher for on-chip caches, (2) Hermes, a perceptron learning-based off-chip predictor for multi-level cache hierarchies, and (3) Sibyl, a reinforcement learning-based data placement policy for hybrid storage system Our evaluation shows that Pythia, Hermes, and Sibyl significantly outperform the best-prior human-designed policies, while incurring modest hardware overheads. Collectively, this article demonstrates that integrating adaptive learning into memory subsystems can lead to intelligent, self-optimizing architectures that unlock performance and efficiency gains beyond what is possible with traditional human-designed approaches.

Even as modern computing systems allow the manipulation and distribution of massive amounts of information, users of these systems are unable to manage the confidentiality of their data in a practical fashion. Conventional access control security mechanisms cannot prevent the illegitimate use of privileged data once access is granted. For example, information provided by a user during an online purchase may be covertly delivered to malicious third parties by an untrustworthy web browser. Existing information-flow security mechanisms do provide this assurance, but only for programmer-specified policies enforced during program development as a static analysis on special-purpose type-safe languages. Not only are these techniques not applicable to many commonly used programs, but they leave the user with no defense against malicious programmers or altered binaries. In this paper, we propose RIFLE, a runtime information-flow security system designed from the user's perspective. By addressing information-flow security using architectural support, RIFLE gives users a practical way to enforce their own information-flow security policy on all programs. We prove that, contrary to statements in the literature, run-time systems like RIFLE are no less secure than existing language-based techniques. Using a model of the architectural framework and a binary translator, we demonstrate RIFLE's correctness and illustrate that the performance cost is reasonable.

The calculation of macroscopic neutron cross-sections is a fundamental part of the continuous-energy Monte Carlo (MC) neutron transport algorithm. MC simulations of full nuclear reactor cores are computationally expensive, making high-accuracy simulations impractical for most routine reactor analysis tasks because of their long time to solution. Thus, preparation of MC simulation algorithms for next generation supercomputers is extremely important as improvements in computational performance and efficiency will directly translate into improvements in achievable simulation accuracy. Due to the stochastic nature of the MC algorithm, cross-section data tables are accessed in a highly randomized manner, resulting in frequent cache misses and latency-bound memory accesses. Furthermore, contemporary and next generation non-uniform memory access (NUMA) computer architectures, featuring very high latencies and less cache space per core, will exacerbate this behaviour. The absence of a topology-aware allocation strategy in existing high-performance computing (HPC) programming models is a major source of performance problems in NUMA systems. Thus, to improve performance of the MC simulation algorithm, we propose a topology-aware data allocation strategies that allow full control over the location of data structures within a memory hierarchy. A new memory management library, known as AML, has recently been created to facilitate this mapping. To evaluate the usefulness of AML in the context of MC reactor simulations, we have converted two existing MC transport cross-section lookup “proxy-applications” (XSBench and RSBench) to utilize the AML allocation library. In this study, we use these proxy-applications to test several continuous-energy cross-section data lookup strategies (the nuclide grid, unionized grid, logarithmic hash grid, and multipole methods) with a number of AML allocation schemes on a variety of node architectures. We find that the AML library speeds up cross-section lookup performance up to 2x on current generation hardware (e.g., a dual-socket Skylake-based NUMA system) as compared with naive allocation. These exciting results also show a path forward for efficient performance on next-generation exascale supercomputer designs that feature even more complex NUMA memory hierarchies.

In the past decade, real-time embedded systems became more and more complex and pervasive. From the user perspective, these systems have stringent requirements regarding size, performance and energy consumption, and due to business competition, their time-to-market is a crucial factor. Besides these requirements, system designers should handle the increasing dynamism that appears in resources required by modern applications, like object-based video coders. In addition, the new architectural features lately introduced in hardware platforms for increasing the average performance enlarge the gap between the average and the worst case execution time of the applications. Therefore, much work is being done in developing design methodologies for embedded systems to deal with the dynamism and to cope with the tight requirements. One of the most well known design methodologies is scenario-based design. It has been used for a long time in user-centered design approaches for different areas, including embedded systems. Scenarios concretely describe, in an early phase of the development process, the use of a future system. Usually, they appear like narrative descriptions of envisioned usage episodes, or like unified modeling language (UML) use-case diagrams which enumerate, from functional and timing point of view, all possible user actions and the system reactions that are required to meet a proposed system function. These scenarios are often called use-case scenarios. In this thesis, we concentrate on a different type of scenarios, so-called ap- plication scenarios, which may be derived from the behavior of the embedded system application. While use-case scenarios classify an application’s behavior based on the different ways the system can be used, application scenarios classify application behavior based on the cost aspects, like quality or resource usage. Application scenarios are used to reduce the system cost by exploiting information about what can happen at runtime to make better design decisions. We have developed a general methodology that can be integrated within existing embedded system design methodologies. It consists of five design time / runtime steps: (i) identification that classifies an application into scenarios; (ii) prediction that generates a runtime mechanism used to find in which scenario the application is running, (iii) exploitation that enables more specific and aggressive design decisions to be made for each scenario, (iv) switching that specifies when and how the application switches from one scenario to another, and (v) calibration that extends and modifies the scenarios and their related mechanisms, based on the runtime collected information, to further improve the system cost and quality. To prove the effectiveness of our methodology, we developed several automatic trajectories that exploit application scenarios for low energy, single processor embedded system design, under both soft and hard real-time constraints. They can automatically classify the runtime behavior of the application into several application scenarios, where the cost (in terms of required processor cycles) within a scenario is always fairly similar. Moreover, a runtime predictor is automatically derived and introduced in the application, and at runtime it is used to select and switch between scenarios, so the different optimizations used for each scenario can be enabled. All of these trajectories are applicable to streaming applications with the dynamism mostly presented in the control variables. These applications are written in C, as C is the most used language to write embedded systems software. They detect and exploit scenarios to improve the cycle budget estimation for applications, reducing the over-estimation in number and size of computation resources in comparison to existing design methods. Moreover, by integrating the application with an automatically derived predictor and using it in the context of a proactive dynamic voltage scaling (DVS) aware scheduler, the amount of used energy is reduced with no or almost no sacrifice in the resulting system quality. This can be achieved by being conservative, as required for hard real-time systems, or by using a runtime calibration mechanism, which works well for soft real-time systems. Even though all the new information about scenarios and the mechanisms introduced in the application add an extra runtime overhead, our methods keep this overhead limited and under control, and generate a final implementation of the application that has a substantial average energy saving.

AbstractÐIn the past decade, the exponential growth in commodity CPU&amp;apos;s speed has far outpaced advances in memory latency. A second trend is that CPU performance advances are not only brought by increased clock rate, but also by increasing parallelism inside the CPU. Current database systems have not yet adapted to these trends and show poor utilization of both CPU and memory resources on current hardware. In this paper, we show how these resources can be optimized for large joins and translate these insights into guidelines for future database architectures, encompassing data structures, algorithms, cost modeling, and implementation. In particular, we discuss how vertically fragmented data structures optimize cache performance on sequential data access. On the algorithmic side, we refine the partitioned hash-join with a new partitioning algorithm called radix-cluster, which is specifically designed to optimize memory access. The performance of this algorithm is quantified using a detailed analytical model that incorporates memory access costs in terms of a limited number of parameters, such as cache sizes and miss penalties. We also present a calibration tool that extracts such parameters automatically from any computer hardware. The accuracy of our models is proven by exhaustive experiments conducted with the Monet database system on three different hardware platforms. Finally, we investigate the effect of implementation techniques that optimize CPU resource usage. Our experiments show that large joins can be accelerated almost an order of magnitude on modern RISC hardware when both memory and CPU resources are optimized. Index TermsÐMain-memory databases, query processing, memory access optimization, decomposed storage model, join algorithms, implementation techniques. 1