Architecture design with STT-RAM: Opportunities and challenges

Spin transfer torque magnetic random access memory (STT-MRAM) is one of the most promising new non-volatile memory technologies. Recently, STT-MRAM has become popular as a DRAM alternative in main memories particularly for tablets and palmtop computers in part due to its non-volatile properties and potential for improved device scalability. However, STT-MRAM is well known for its asymmetric access properties and considerable attention has been applied to the device, circuit, and architecture designs to mitigate its write energy concerns. In this work, we propose a new method to reduce the write energy consumption using a combination of pulse width scaling and error correction coding schemes for STT-MRAM main memories. The introduced methodology works by dynamically adjusting the pulse width based on the compressibility of the written data. We evaluate the efficiency of the proposed method on Android applications. Experimental results show an average improvement of more than 10% in the write energy consumption, in addition to the 46% reduction achieved by compression.

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising emerging memory technology for on-chip caches. It has a low read access time and low leakage power. Unfortunately, however, STT-MRAM suffers from its long write latency and high write energy consumption. This paper proposes a cache management technique called Proactive Invalidation (PROI) that proactively invalidates dead blocks in advance to enable fast writes in the STT-MRAM caches. Experimental evaluation shows that the proposed technique improves performance by 14% on average compared to the baseline STT-MRAM cache. This paper also proposes two optimization techniques called Proactive Invalidation-aware Data Encoding (PIDE) and Narrowness-aware Partial Write (NPW) to minimize the energy overheads of Proactive Invalidation. Experimental results demonstrate that the total energy consumption of the STT-MRAM cache with PROI is only 1.8% higher than the baseline when PROI is applied with PIDE and NPW.

Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate for next generation memory as it is non-volatile, fast, and has unlimited endurance. Another important aspect of STT-MRAM is that its core component, the nanoscale magnetic tunneling junction (MTJ), is thought to be radiation hard, making it attractive for space and nuclear technology applications. However, studies on the effects of ionizing radiation on the STT-MRAM writing process are lacking for MTJs with perpendicular magnetic anisotropy (pMTJs) required for scalable applications. Particularly, the question of the impact of extreme total ionizing dose on perpendicular magnetic anisotropy, which plays a crucial role on thermal stability and critical writing current, remains open. Here we report measurements of the impact of high doses of gamma and neutron radiation on nanoscale pMTJs used in STT-MRAM. We characterize the tunneling magnetoresistance, the magnetic field switching, and the current-induced switching before and after irradiation. Our results demonstrate that all these key properties of nanoscale MTJs relevant to STT-MRAM applications are robust against ionizing radiation. Additionally, we perform experiments on thermally driven stochastic switching in the gamma ray environment. These results indicate that nanoscale MTJs are promising building blocks for radiation-hard non-von Neumann computing.

The Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) has been identified, by the International Technology Roadmap for Semiconductors (ITRS), as one of the most promising emerging technology. Different works handled the retention and reliability of STT-MRAM. However, to the best of our knowledge, the impact of a pulsed laser beam on STT-MRAM reliability and security has not been investigated so far as proposed in this paper. Since STT-MRAM are Back-end Of Line devices, we exposed the bit cells from the front-side to a 1064 nm wavelength laser pulse. The devices are electrically characterized (switching conditions between the two logical states) before and after the laser irradiation. The main result of this study is the demonstration of a resistance switching from Anti-Parallel (AP) to Parallel (P) state after the laser irradiation. That is how data integrity was altered by this irradiation, flipping the bit stored in this memory.

Spin transfer torque magnetic random access memory (STT-MRAM) is an emerging memory technology which exhibits nonvolatility, high density, high endurance, and nano-second read and write times. These characteristics make STT-MRAM suitable for last-level cache and other embedded applications. The STT-MRAM bit-cell consists of a magnetic tunnel junction (MTJ) which is composed of two ferromagnetic layers (free and fixed layers) and one insulating layer in between. As STT-MRAM arrays become denser to meet cost and requirements of high performance computing, the distance between adjacent MTJ bits reduces. This aggravates the magnetic coupling from free and fixed layer of one MTJ bit to its neighbors. Even though magnetic coupling is expected to become stronger as MTJ scales down, its impacts on static and dynamic properties on MTJ is relatively unexplored. In this paper, we present a model of the magnetic field coupling in high-density MTJ arrays for three different types of MTJ stacks and evaluate the effect of magnetic field induced coupling on static and dynamic properties. Lastly, we show how process induced variations in MTJ characteristics affect the magnitude of magnetic coupling and their effect on the electrical characteristics of the STT-RAM arrays.

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging non-volatile memory technology, as a leading candidate to replace conventional on-chip memories due to its various advantages such as high density, non-volatility, scalability, high endurance and CMOS compatibility. However, read and write operations in STT-MRAM are extremely vulnerable to manufacturing variations. In particular, the read operation is becoming more susceptible to failures since the read timing and read-disturb failures have conflicting requirements of read period. To overcome this issue, we propose a technique to reduce the read period without sacrificing the target reliability requirements. The reduced read period, in turn, results in improved read performance and reduced read-disturb rates. The results show that using this technique, the read period can be reduced by 50%, and the read-disturb probability by 51%.

A new class of spin-transfer torque magnetic random access memory (STT-MRAM) is discussed, in which writing is achieved using thermally initiated magnonic current pulses as an alternative to conventional electric current pulses. The magnonic pulses are used to destabilize the magnetic free layer from its initial direction, and are followed immediately by a bipolar electric current exerting conventional spin-transfer torque on the free layer. The combination of thermal and electric currents greatly reduces switching errors, and simultaneously reduces the electric switching current density by more than an order of magnitude as compared to conventional STT-MRAM. The energy efficiency of several possible electro-thermal circuit designs have been analyzed numerically. As compared to STT-MRAM with perpendicular magnetic anisotropy, magnonic STT-MRAM reduces the overall switching energy by almost 80%. Furthermore, the lower electric current density allows the use of thicker tunnel barriers, which should result in higher tunneling magneto-resistance and improved tunnel barrier reliability. The combination of lower power, improved reliability, higher integration density, and larger read margin make magnonic STT-MRAM a promising choice for future non-volatile storage.

Due to high static power and low scalability, the traditional SRAM-based cache is not a good solution for image processing applications. Emerging spin transfer torque magnetic RAM (STT-MRAM) is a promising candidate for cache due to its low leakage power and high density. However, STT-MRAM suffers from high write energy. Therefore, by making use of the ability of tolerating minor errors in image processing applications, this work presents an STT-MRAM-based <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">APP</monospace> roximate <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cache</monospace> architecture ( <monospace xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">APPcache+</monospace> ) to write/read approximate data, which can largely reduce the cache energy and improve the STT-MRAM lifetime. APPcache+ includes three main designs. First, we find that there are many similar elements (e.g., pixels in images) in cache lines. Therefore, APPcache+ presents several lightweight similarity-based encoding techniques to remove redundant elements, thus, shortening the data size and reducing the energy of STT-MRAM cache. Second, we design a partial read scheme to reduce the read energy of the STT-MRAM cache. In the traditional decompression process, the whole line is fetched into the decompressor, leading to unnecessary read energy. The partial read scheme can largely reduce read energy while keeping the overhead low. Third, we observe the encoding schemes may lead to bit write imbalance. Therefore, we propose a lightweight Ping-Pong intraline wear-leveling scheme to improve the lifetime. Compared with the baseline, extensive evaluation results show that our APPcache+ can largely reduce the overall energy by 32.58%, improve lifetime by 40.7% with only 2.2% performance degradation, and 1.86% output quality loss.

Due to the leakage power of CMOS-based memory, Nonvolatile magnetic memory is considered a strong candidate to replace the CMOS-based memory. Spin transfer torque magnetic random access memory (STT-MRAM) is one of the most promising candidates, but it still has many shortcomings related to the write operation. Compared to STT-MRAM, spin orbit torque magnetic random access memory (SOT-MRAM) is the next generation of nonvolatile magnetic memory because of its relatively good performance and low power. Although SOT-MRAM has various advantages over STT-MRAM, a significant reduction in write power is required to meet the power level of CMOS-based memory. In this paper, we present a low power SOT-MRAM cell configuration using the dual write operation. By writing on two cells simultaneously, write energy can be reduced depending on data patterns. Compared to the conventional 2T-1MTJ SOT-MRAM, the proposed SOT-MRAM cell with the dual write scheme reduces the write energy by 26.3% on average.

Spin Transfer Torque Magnetic RAM (STT-MRAM) is one of the most promising on-chip technologies, which delivers high density, non-volatility, and near-zero leakage power. However, Spin Transfer Torque Magnetic RAM (STT-MRAM) suffers from three reliability issues, namely, read disturbance, write failure, and retention failure, that present significant challenges to its use as a reliable on-chip memory. All of these three reliability challenges become even more threatening with any increase in STT-MRAM cell temperature. Write operations are regarded as the main source of heat generation and temperature increase in STT-MRAM on-chip memories. This article first presents experiments to show how the heat generated by consecutive writes affects the reliability of an STT-MRAM on-chip cache. Then, it proposes the WiSE framework, an approach to reduce the STT-MRAM-based cache memory temperature and improve its reliability. WiSE utilizes the Reinforcement Learning (Reinforcement Learning (RL)) technique to detect high-density write operation patterns in STT-MRAM cache. To manage the write operations across the STT-MRAM caches, WiSE introduces a new temperature-aware replacement policy. The simulation results show that while WiSE imposes only about 1% performance overhead, it improves retention failure rate, read disturbance rate and write failure rate by 64%, 57%, and 47%, respectively, compared to Least Recently Used (Least Recently Used (LRU)) replacement policy.

Due to the memory wall in conventional Von-Neumann computer architectures, the limited bandwidth between processors and memories has become one of the most critical bottlenecks to improve system performance. With the emerging of non-volatile memories, the computing-in-memory (CIM) paradigm has regained interest to tackle the issue at the architecture level. CIM can effectively alleviate the stress on the limitted bandwidth by performing logic operations within memories. However, CIMs are not yet studied carefully at the circuit level, and even its reliability and performance. In this paper, we proposed a CIM implementation: dual reference (DualRef) scheme at the circuit level within STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) array. Simulations were carried out to verify the functionality and assess the reliability and performance of DualRef scheme in terms of operation error rate, sensing margin, operation delay and dynamic energy consumption. Simulation results validate DualRef scheme and reveal that it is reliable to perform bitwise logic opertions within STT-MRAM while the TMR (Tunnel Magnetoresistance Ratio) varying between 100% and 300% and supply voltage Vdd varying from 0.9V to 1.2V. This work provides a robust circuitry scheme and design space to effectively implement CIM in STT-MRAM.

Spin-transfer torque magnetic random access memory (STT-RAM) technology has emerged as a potential replacement of SRAM in cache design, especially for building large-scale and energy-efficient last level caches. Compared with single-level cell (SLC), multi-level cell (MLC) STT-RAM is expected to double cache capacity and increase system performance. However, the two-step read/write access schemes incur considerable energy consumption and performance degradation. In this paper, we propose two techniques using data compression to optimize MLC STT-RAM cache design. The first technique tries to compress a cache line and fit it into only the soft-bit region of the cells, so that reading or writing this cache line takes only one step which is fast and energy-efficient. We introduce a second technique to increase the cache capacity by enabling the left hard-bit region to store another compressed cache line, which can improve the system performance for memory intensive workloads. The experimental results show that, compared with a conventional MLC STT-RAM last level cache design, our overhead minimized technique reduces the dynamic energy consumption by 38.2% on average with the same system performance, and our capacity augmented technique boosts the system performance by 6.1% with 19.2% dynamic energy saving on average, across the evaluated multi-programmed benchmarks.

Random Access Memories: Magnetic

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is an emerging memory technology, which is seen as a promising replacement for CMOS based on-chip memories. It has several distinctive advantages such as nonvolatility, high endurance, high density, CMOS compatibility and scalability among others. However, retention failure has emerged as a major reliability concern for this technology due to the large variations in retention time because of process variations and temperature effects. The conventional solution to mitigate retention failures is to use scrubbing at regular intervals to prevent accumulation of errors, based on the worst case retention time of the memory array. But this leads to large performance and energy overheads. In this work, we propose a process variation and temperature aware scrubbing technique, where we cluster the cache lines into different groups based on their retention times and use different scrubbing intervals for each of these groups. In addition, the scrubbing interval is adjusted at run-time based on the operating temperature, to guarantee target error rate requirements. Our results show that for a 512KB cache, a group size of 4 can reduce the performance and dynamic energy overheads of scrubbing by 97%, under the same error rate constraint.

The single event upset hardened design of spin transfer torque magnetic random access memory read circuits at 40 nm technology