Architecture optimization of a finite impulse response filter using toggle-based power estimation

PurposeTraditionally, each time a new design for a finite impulse response (FIR) filter is required, a new algorithm has to be developed specially for the FIR filter. Furthermore, corresponding hardware architecture must be designed specially to meet the requirement of the FIR specifications. The purpose of this paper is to propose an arithmetic logic unit (ALU)‐based universal FIR filter suitable for realization in field programmable gate arrays (FPGA), where various FIR filters can be implemented just by programming instructions in the ROM with identical hardware architecture.Design/methodology/approachRather than multiplier‐accumulator‐based architecture for conventional FIR, the proposed ALU architecture implements the FIR functions by using accumulators and shift‐registers controlled by the instructions of ROM. Furthermore, time division multiplexing access (TDMA) technique is employed to reduce the chip size. In addition, the proposed FIR architecture is verified in a SOC hardware and/or software co‐emulation system.FindingsAn ALU‐based universal FIR filter suitable for realization in FPGA is designed and verified in a SOC hardware/software co‐emulation system with example of a 64‐tap FIR filter design.Originality/valueA software‐based design method as well as TDMA scheme for the ALU‐based FIR filter are introduced, making FIR filter architecture universal, programmable, and consuming less FPGA resources.

Digital filters play a central role in modern Digital Signal Processing (DSP) systems. Finite Impulse Response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

Digital filters play a central role in modern digital signal processing (DSP) systems. Finite impulse response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

Background/Objectives: FIR filters play a vital role in signal processing applications. This research work presents a low power and high speed efficient buffer based Distributed Algorithms and it is analyzed with Electro Cardio Gram (ECG) signal Finite Impulse Response (FIR) filter design. Methods/Statistical Analysis: The proposed FIR filter is designed using buffer based DA and it is simulated and synthesized using Cadence digital labs. This is compared with different architectures such as conventional DA, separated look up table DA and LUT less DA. Findings: Synthesis report shows that the proposed design has 52% less power dissipation compared with the conventional DA, 21% reduction in delay with separated Look Up Table (LUT) DA and 8% reduction in area with LUT less DA. Conclusion/Improvements: Presently this method is applied for ECG signal input with 16-tap FIR filter. This can be extended for higher order filters to achieve better performance.

WITHDRAWN: An Optimistic Design of 16-Tap FIR Filter with Radix-4 Booth Multiplier Using Improved Booth Recoding Algorithm

A bit-oriented architecture for the digital finite impulse response (FIR) filter with adaptive coefficients is presented. Instead of using multipliers, the FIR operation is regarded as the summation of a larger number of operands. The architecture utilises two new word-level operand compressors, namely six-to-triple and six-to-double compressors. Both of these two compressors, multiple operands can be merged efficiently without long carry propagation. Using such compressors as the basic building blocks, a FIR filter can be implemented as a fast and regular structure that lends itself to automation. Experiments show that the FIR generator based on the proposed architecture could easily achieve a 44% power reduction as compared to the traditional high-speed transposed form.

In this paper one method of optimizing a digital finite impulse response (FIR) filter has been illustrated. The advantages and disadvantages of several architectures and of the circuit modeling were presented using a standard toggle-based method for the circuit power estimation, gate-level simulations and synthesis. We showed that we can achieve a significant power reduction from the beginning by carefully selecting the right architecture and optimizing the VHDL code description of the module. The analysis was made based on the unity delay model and not on the physical extracted layout for a 150nm technology but the method can be used for other technologies as well.

In Digital wireless communication system Finite Impulse Response (FIR) filter is used fundamentally pipelined as well as support Multiplication with Accumulation scheme (MAC) that results in important save of calculation. Efficient area along with delay recognition of great order FIR filters for update applications have been achieved by the opportunity of recognition of block FIR filter in transpose form organization. The projected transpose form block filter of update applications are developed by a general carry select adder based architecture. Secured digital FIR filter block is implemented by a pepped-up design using the MAC scheme. Booth multiplier has been used in MAC scheme. The proposed method has less area also delay than conventional filter.

We present algorithmic and architectural transforms for low power realization of Finite Impulse Response (FIR) filters implemented both in software on programmable DSPs and as hardwired macros. For the programmable DSP based implementation, these transform address power reduction in the program memory address and data busses and also the multiplier. We also propose architectural extensions to support some of these transformations. The transforms for hardwired FIR filters aim at reducing the supply voltage while maintaining the throughput. We also present transforms that reduce the computational complexity of the FIR filter computation and thus achieve power reduction.

Time-interleaved analog-to-digital converter (TIADC) mismatch compensation filters are traditionally finite impulse response (FIR) filters. The advantages of using FIR filters are that FIR filters are inherently stable and that the design techniques are readily available. In this paper, we show that, infinite impulse response (IIR) mismatch compensation filters with guaranteed stability can be designed and for the same total number of coefficients, the IIR filters achieve better mismatch compensation than their FIR counterparts. We also show that for a given spurious frequency power, our new IIR TIADC compensation filter yields more than 30% saving in the total number of multiplier coefficients when compared to the conventional FIR TIADC compensation filters.

Nowadays, the communications and computations has been performed by Digital Finite Impulse Response (FIR) filter. FIR filter is predominantly used in DSP applications for efficient implementations. FIR filter is able to declare a firm linear phase frequency characteristic with any type of amplitude frequency characteristic in a DSP system. A reconfigurable FIR filter architecture has been implemented using Least Mean Square (LMS) algorithm in the proposed scheme. The proposed scheme achieves better performance when compared to an existing scheme. The proposed method has been implemented in ModelSim tool and efficiency has been calculated by using the device Virtex 6 Low Power in Xilinx ISE Design Suite 12.4.

Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes.

Fractional sample interpolation with finite impulse response (FIR) filters is commonly used for motion-compensated prediction (MCP). The FIR filtering can be viewed as a signal decomposition using restricted basis functions. The concept of generalized interpolation provides a greater degree of freedom for selecting basis functions. We developed a generalized interpolation framework for MCP using fixed-point infinite impulse response and FIR filters. An efficient multiplication-free design of the algorithm that is suited for hardware implementation is shown. A detailed analysis of average and worst case complexities compared to FIR filter-based interpolation techniques is provided. Average bitrate savings of around 2.0% compared to an 8-tap FIR filter are observed over the high-efficiency video coding dataset at a similar worst case complexity.

Chapter 2 - Design and Implementation of Digital FIR Filters

Recent trends in mobile computing and multimedia application demand low power digital signal processing systems (DSP). The most important block in any DSP system is a finite impulse response (FIR) filter. Here a reliable low power FIR filter is designed using Vedic multipliers which specifically perform addition and shifting operation. The addition is done using full adder with 9 transistors which use only 3 transistor XOR gate. A four tap FIR filter was implemented in microwind 2 electronic design automation tool using CMOS 90nm technology. In the proposed design the power consumption is reduced by 23% and delay has been reduced by 44% when compared with the existing FIR filters.