Architectures of FPGA-Based Hardware Accelerators and Design Techniques

In this modern technology era, in System on Chip (SoC) design, performance of processing units in computer is always on demand. By having hardware accelerators in computer system, core processor can offload task to it and this creates parallel execution to improve the processing speed. One of the functional blocks that are crucial in Hardware Accelerator's design is Storage Unit, which is used to keep data that is needed for processing or either the processed data. Under conventional hardware accelerator's design, the storage architecture is shaped to suit a certain processing algorithm and this introduced less flexibility in SoC design. In this paper, a novel design of storage architecture that is able to handle multiple accelerator engines and also modular to typical specification of hardware accelerators has been implemented.

With the expansion of Convolutional Neural Networks (CNNs) applications in various domains such as autonomous driving and real-time data processing, the demand for efficient computational resources has increased dramatically. Traditional computing platforms such as CPUs struggle to manage the complex and data-intensive tasks required by modern CNNs. This paper delves into the development and system optimization of dedicated hardware accelerators - GPUs, FPGAs, and ASICs to meet these demands. Through innovative architectural design and optimization techniques, these gas pedals improve computational speed and energy efficiency. Our study demonstrates that through these optimizations, the processing efficiency of hardware accelerators is significantly improved while energy consumption is effectively controlled, setting a new standard for the design of future hardware accelerators for convolutional neural networks. In addition, I discuss practical applications and future challenges, providing a comprehensive overview of current technologies and their potential development. This research highlights the critical role of advanced hardware accelerators in enabling the next generation of AI applications, ensuring technological advancement and sustainability in high-demand computing environments.

Design of exact reduct rough set hardware accelerator for early-stage diabetes risk prediction

In the July 2016 issue of IEEE Consumer Electronics Magazine, the Hardware Matters column discussed intellectual property (IP) cores, and several articles have been presented that discoursed on topics ranging from the evolution of IP core design, to the protection of IP cores, to high-level perspectives on IP cores. In all of these articles, the resiliency aspect of IP core design has not been touched upon. In this issue?s column, I intend to present a deep cognizance to IEEE Consumer Electronics Magazine readers regarding the resiliency aspects of IP cores against terrestrial transient faults, which are seen as a major contributing factor to the eventual malfunctioning of integrated circuits (ICs).

Hardware accelerators are playing an increasingly important role in the field of computer science and engineering, especially in accelerating deep learning and large-scale data processing. However, the traditional hardware accelerator design often relies on manual adjustment and experience accumulation, which is inefficient. Therefore, the use of machine learning technology to optimize hardware accelerator design has become a new trend. In this paper, a hardware accelerator optimization design method based on machine learning is proposed, including hardware design, algorithm optimization, system-level optimization, and deep learning model compression. Through the research and verification of the actual case, this research proves the effectiveness and feasibility of the hardware accelerator optimization design method based on machine learning. Compared with the traditional design method, this method can find better design scheme in shorter time and has higher performance prediction accuracy. Therefore, this method can significantly improve the design efficiency and performance of hardware accelerators. The results of this study are of great significance for promoting the development of hardware accelerator technology. It can promote scientific research and engineering applications in related fields to make greater progress, and promote the development of artificial intelligence, big data processing and other fields.

Low power & mobile hardware accelerators for deep convolutional neural networks

Homomorphic Encryption (HE) allows performing specific algebraic computations on encrypted data without the need for decryption. For this reason, HE is emerging as a strong privacy-preserving solution in cloud computing environments since it allows to keep data secure even in the case the cloud server is not trusted. HE libraries such as Microsoft SEAL have been recently released; however, such libraries are not specifically designed for resource-constrained platforms and they are often expensive in terms of computational resources and memory consumption, which limits their usage in edge devices. This limitation is contained by the SEAL-Embedded library, the first C-based HE library specifically designed for embedded platforms. In this article, we propose a hardware accelerator specifically designed for the SEAL-Embedded library and its implementation of the CKKS scheme: the proposed hardware presents a configurable Number Theoretic Transform (NTT) unit for all the polynomial degrees available on the SEAL-Embedded, a memory architecture able to reduce the I/O latency and a dedicated module for the generation of roots of unity. A complete system that includes a 32-bit RISC-V processor has been implemented on a Xilinx ZCU106 FPGA board to test the functionality of the hardware accelerator and to measure performance improvements. The results showed a speed-up of around x1000 with the hardware acceleration respect to the pure software implementation of the SEAL-Embedded library for the symmetric encryption function.

With the emergence of commodity multicore architectures, exploiting tightly-coupled parallelism has become increasingly important. Functional programming languages, such as Haskell, are, in principle, well placed to take advantage of this trend, offering the ability to easily identify large amounts of fine-grained parallelism. Unfortunately, obtaining real performance benefits has often proved hard to realise in practice. This paper reports on a new approach using middleware that has been constructed using the Eden parallel dialect of Haskell. Our approach is "low pain" in the sense that the programmer constructs a parallel program by inserting a small number of higher-order algorithmic skeletons at key points in the program. It is "high gain" in the sense that we are able to get good parallel speedups. Our approach is unusual in that we do not attempt to use shared memory directly, but rather coordinate parallel computations using a message-passing implementation. This approach has a number of advantages. Firstly, coordination, i.e. locking and communication, is both confined to limited shared memory areas, essentially the communication buffers, and is also isolated within well-understood libraries. Secondly, the coarse thread granularity that we obtain reduces coordination overheads, so locks are normally needed only on (relatively large) messages, and not on individual data items, as is often the case for simple shared-memory implementations. Finally, cache coherency requirements are reduced since individual tasks do not share caches, and can garbage collect independently. We report results for two representative computational algebra problems. Computational algebra is a challenging application area that has not been widely studied in the general parallelism community. Computational algebra applications have high computational demands, and are, in principle, often suitable for parallel execution, but usually display a high degree of irregularity in terms of both task and data structure. This makes it difficult to construct parallel applications that perform well in practice. Using our system, we are able to obtain both extremely good processor utilisation (97%) and very good absolute speedups (up to 7.7) on an eight-core machine.

Advances in computer networking and database technologies have enabled the collection and storage of vast quantities of data. Data mining can extract valuable knowledge from this data, and organizations have realized that they can often obtain better results by pooling their data together. However, the collected data may contain sensitive or private information about the organizations or their customers, and privacy concerns are exacerbated if data is shared between multiple organizations.Distributed data mining is concerned with the computation of models from data that is distributed among multiple participants. Privacy-preserving distributed data mining seeks to allow for the cooperative computation of such models without the cooperating parties revealing any of their individual data items. Our paper makes two contributions in privacy-preserving data mining. First, we introduce the concept of arbitrarily partitioned data, which is a generalization of both horizontally and vertically partitioned data. Second, we provide an efficient privacy-preserving protocol for k-means clustering in the setting of arbitrarily partitioned data.

It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mechanisms, such as barriers. Support for fine-grain synchronization on individual data items becomes notably important in order to efficiently exploit thread-level parallelism available on multi-threading and multi-core processors. Fine-grained synchronization can be achieved using the full/empty tagged shared memory. We define the complete set of synchronizing memory instructions as well as the architecture of the full/empty tagged shared memory that provides support for these operations. We develop a snoopy cache coherency protocol for an SMP with the centralized full/empty tagged memory.

This dissertation describes research activities broadly concerning the area of High-level synthesis (HLS), but more specifically, regarding the HLS-based design of energy-efficient hardware (HW) accelerators. HW accelerators, mostly implemented on FPGAs, are integral to the heterogeneous architectures employed in modern high performance computing (HPC) systems due to their ability to speed up the execution while dramatically reducing the energy consumption of computationally challenging portions of complex applications. Hence, the first activity was regarding an HLS-based approach to directly execute an OpenCL code on an FPGA instead of its traditional GPU-based counterpart. Modern FPGAs offer considerable computational capabilities while consuming significantly smaller as compared to high-end GPUs. Several different implementations of the K-Nearest Neighbor algorithm were considered on both FPGA- and GPU-based platforms and their performance was compared. FPGAs were generally more energy-efficient than the GPUs in all the test cases. Eventually, we were also able to get a faster (in terms of execution time) FPGA implementation by using an FPGA-specific OpenCL coding style and utilizing suitable HLS directives. The second activity was targeted towards the development of a methodology complementing HLS to automatically derive optimization directives (also known as power intent) from a system-level design description and use it to drive the design steps after HLS, by producing a directive file written using the common format (CPF) to achieve shut-off (PSO) in case of an ASIC design. The proposed LP-HLS methodology reduces the design effort by enabling designers to infer low information from the system-level description of a design rather than at the RTL. This methodology required a SystemC description of a generic management module to describe the design context of a HW module also modeled in SystemC, along with the development of a tool to automatically produce the CPF file to accomplish PSO. Several test cases were considered to validate the proposed methodology and the results demonstrated its ability to correctly extract the low information and apply it to achieve optimization in the backend flow.

ARTICo3 is an architecture that permits to dynamically set an arbitrary number of reconfigurable hardware accelerators, each containing a given number of threads fixed at design time according to High Level Synthesis constraints. However, the replication of these modules can be decided at runtime to accelerate kernels by increasing the overall number of threads, add modular redundancy to increase fault tolerance, or any combination of the previous. An execution scheduler is used at kernel invocation to deliver the appropriate data transfers, optimizing memory transactions, and sequencing or parallelizing execution according to the configuration specified by the resource manager of the architecture. The model of computation is compatible with the OpenCL kernel execution model, and memory transfers and architecture are arranged to match the same optimization criteria as for kernel execution in GPU architectures but, differently to other approaches, with dynamic hardware execution support. In this paper, a novel design methodology for multithreaded hardware accelerators is presented. The proposed framework provides OpenCL compatibility by implementing a memory model based on shared memory between host and compute device, which removes the overhead imposed by data transferences at global memory level, and local memories inside each accelerator, i.e. compute unit, which are connected to global memory through optimized DMA links. These local memories provide unified access, i.e. a continuous memory map, from the host side, but are divided in a configurable number of independent banks (to increase available ports) from the processing elements side to fully exploit data-level parallelism. Experimental results show OpenCL model compliance using multithreaded hardware accelerators and enhanced dynamic adaptation capabilities.

Neural networks have been widely deployed in a number of applications due to their strong learning and feature extraction ability. To meet the ever increasing accuracy requirements from various applications, neural network models have become more complicated and diversified by exploiting more layers, larger model size, and more diverse functions. As a result, the design of application specified hardware accelerators for neural networks is also becoming more difficult, especially for real-time embedded applications. To efficiently bridge the gap between algorithm and hardware design phases, a pre-RTL neural network simulator (SimuNN) is proposed in this paper to enable early phase verification and fast prototyping. SimuNN can be used for inference, simulation and also evaluation, results of which can guide the design of both neural network models and hardware accelerators. SimuNN supports inference in various data precision, and is compatible with TensorFlow, which makes it easy for platform migration. It provides multi-level trace results that can be taken as the gold model of RTL designs. Moreover, the hardware performance under various quantizations, dataflow organizations and hardware configurations can be evaluated by SimuNN based on a generalized hardware model. Based on that, two dataflow organization schemes are concluded for determining the optimal configurations of hardware architecture under various hardware and performance constraints.

This article designs a Yolov4 Tiny convolutional neural network hardware accelerator based on FPGA. A four-stage pipeline convolutional array structure has been proposed. In the design, the NC4HW4 parameter rearrangement and Im2col dimensionality reduction algorithm are used as the core to maximize the parallelism of matrix operations under limited resources. Secondly, a PE convolutional computing unit structure was designed, and a resource-efficient and highly reliable convolutional computing module was implemented by combining INT8 DSP resource reuse technology. Finally, the accelerator will be deployed on Xilinx’s Zynq7030 development board. The experimental results show that at a clock frequency of 130 MHz, the power consumption of the hardware accelerator is only 2.723 W, and the performance is 59.54 Gbps. Compared with related research, it has improved more than 2.1 times. This accelerator can complete hardware-accelerated computing tasks in object detection with high energy efficiency.

Real-world experiences with generating real-world evidence: Case Studies from PCORI's pragmatic clinical Studies program