Area-Efficient Capacitor-Splitting Switching Scheme with a Nearly Constant Common-Mode Voltage for SAR ADCs

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A novel area-efficient switching scheme is proposed for the successive approximation register (SAR) analog-to-digital converters (ADCs). The capacitor-splitting structure, charge-average switching technique, and [Formula: see text] (equal to [Formula: see text]/4) are combined together and optimized to realize the proposed switching scheme. [Formula: see text] is only used in the last two bit cycles, which affects the ADC accuracy little and reduces capacitor area by half. It achieves a 98% less switching energy and an 87.5% less capacitor area compared with the conventional switching method. In addition, the DAC output common-mode voltage is approximately constant. Thus, the proposed switching method is a good tradeoff among power consumption, capacitor area, DAC output common-mode voltage, and ADC accuracy. The proposed SAR ADC is simulated in 0.18[Formula: see text][Formula: see text]m CMOS technology with a supply voltage of 0.6[Formula: see text]V and at a sampling rate of 20[Formula: see text]kS/s. The signal-to-noise-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 58.2 and 73.7[Formula: see text]dB, respectively. The effective number of bits (ENOB) is 9.4. It consumes 42[Formula: see text]nW, resulting in a figure-of-merit (FoM) of 3.11 fJ/conversion-step.