Area minimization of clock distribution networks using local topology modification

The deferred-merge embedding (DME) algorithm is presented. In linear time, it embeds any given connection topology into the Manhattan plane to create a clock tree with zero skew while minimizing total wirelength. Experimental results show that the algorithm yields exact zero skew trees with 9% to 16% wirelength reduction over previous constructions. The DME algorithm may be applied to either the Elmore or the linear delay model and yields optimal total wirelength for linear delay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this study a new approach for skew compensation in energy recovery clock distribution networks is introduced by manipulating the operating speed of the flip-flops. The STMicroelectronics 90 nm technology allows the use of devices with different threshold voltages, namely: high threshold voltage (HVT), standard threshold voltage (SVT) and low threshold voltage (LVT). Three types of flip-flops of equal input load: fast , standard and slow are used. Timing parameters of the flip-flops are adjusted by manipulating the switching threshold of the clock port of the flip-flops. A fast/slow flip-flop has a shorter/longer T DQ delay, compared with a standard flip-flop for the same setup time (T DCLK ). Distributing flip-flops according to their delay requirements would reduce the effect of the clock's skew on the outputs of sequentially adjacent flip-flops. Owing to the slow rise time of the sinusoidal clock signal used in energy recovery clock distribution networks compared to the conventional square-wave clock, the skew that can be compensated for in energy recovery clock distribution networks using this approach would be much higher than in square-wave clock distribution networks. This approach increases the skew bounds required by algorithms to balance the skew in the clock tree leading to reduced design complexity. Theoretical analysis and simulation results using STMicroelectronics 90 nm technology at a clock frequency of 500 MHz show that this approach is feasible and effective where a skew of up to 6.2% 1of the clock period can be compensated for in the example used. In addition, constructing clock trees using the skew slack provided in the proposed technique in a new modified differed merge embedding (DME) algorithm on five benchmarks have shown that the proposed technique enables an average reduction of 11.5% in total wire length and 53.2% reduction in the number of wire elongations. Balancing the skew in the clock tree using buffers was not considered here since inserting a buffer in the clock's path eliminates the energy recovery property. As an example of illustrating the proposed methodology, the authors have used the Elmore delay model with a selected energy recovery flip-flop to verify the practicality of the proposed scheme. Better results can be obtained by using different flip-flops. The method can generally be applied to energy recovery or square-wave clocking if different flip-flops of various speeds are used.

The first stage in channel routing is that of computing a routing solution S, for a given channel with as few tracks as possible. We consider a second stage in which it is desirable to reduce the total wire length without increasing area of routing. In this paper we propose efficient polynomial time algorithms for appreciably reducing the total wire length in two-, three- and multi-layer routing solutions by permuting tracks in the solution S obtained in the first stage. This results in a routing solution that is economical in terms of area as well as total wire length. Our algorithms are particularly important in practical terms since the problem of minimizing the total wire length in a routing solution is NP-hard.

Behavior maintained by intravenously delivered alfentanil, cocaine, or ketamine was assessed using a fixed-ratio schedule of reinforcement. As the dose of each drug was increased, rate of responding also increased up to a maximum. Further increases in dose resulted in decreased response rates (inverted U-shaped curve). An analysis of postreinforcement-pause-time and run-time measures for the ascending limb of the inverted U-shaped functions revealed that behavior was characterized by systematic decreases in both pause time and run time as dose and rate increased. An examination of the descending limb of the dose-response functions revealed that lowered response rates for cocaine and ketamine were correlated with increases in run time and small and inconsistent effects on postreinforcement pause time. Behavior maintained by rate-reducing doses of alfentanil was characterized by lengthened postreinforcement pauses with small increases in run time. These data suggest that at larger doses, drug reinforcers may have unconditioned or direct effects on the behavior that the drug is maintaining, and more important, that the nature of these unconditioned effects depends on the drug that is maintaining behavior.

In the routing design of interposer and etc., the combination of a pin pair to be connected by wire is often flexible, and the reductions of the total wire length and the length difference are pursued to keep the circuit performance. Even though the total wire length can be minimized by finding a minimum cost maximum flow in set pair routing problems, the length difference is often large, and the reduction of it is not easy. In this paper, an algorithm that reduces the length difference while keeping the total wire length small is proposed. In the proposed algorithm, an initial routing first obtained by a minimum cost maximum flow. Then it is modified to reduce the maximum length while keeping the minimum total wire length, and a connection of the minimum length is detoured to reduce the length difference. The effectiveness of the proposed algorithm is confirmed by experiments.

This paper presents a new detialed router for the hierarchical field programmable gate arrays (H-FPGAs). The optimal objectives of proposed routing algorithm are improving the time consumption of routing procedure (minimizing the running time of algorithm), and at the same time make great effort to decrease the wire length and critical path delay. Initially, nets are routed sequentially according to their criticalities. Then, to achieve optimization targets, the nets violating routablity constrains are resolved iteratively by a rip-up and rerouting router using the simulated evolution optimization technique, where each net will be evaluated via a rip-up priority function consisting of the timing part and the congestion part, and then compared to a random number to decide if it will be ripped and rerouted. An experimental result under commercial H-FPGA shows that our router can have about 26% improvement on the time-consumption and 0.45% reduction on total wire length when compared with a modified VPR.

Consider a set of n pins and $n( n - 1 )/2$ specified numbers of wire connections between all pairs of the n pins There are also n holes all in a line with adjacent holes at unit distances apart. The problem is to put the n pins into the n holes such that the total wire length is a minimum. We can abstract the pins and wire connections as a graph G with n nodes and numbers associated with the arcs. For an arbitrary G, we establish a lower bound on the total wire length. If G is a rooted tree, an algorithm is presented which requires $O( {n\log n} )$ operations.

Koch fractal monopole antennas are known to exhibit lower resonant frequencies than Euclidean monopoles of the same height. It has been concluded that there exists a unique relationship between the antenna's fractal geometry and its electromagnetic behavior. Here, the performance properties of the Koch fractal monopole are examined and compared with the performance properties of other bent wire geometry monopoles having the same total wire length and overall height. It is demonstrated that monopoles with less complex shapes exhibit lower resonant frequencies because they are more effective at increasing the electrical volume of the antenna. When these antennas are made to be resonant at the same frequency, they exhibit virtually identical performance properties independent of differences in their geometric shape and total wire length. It is also demonstrated that the effective height of these monopoles converge to that of an electrically small Euclidean monopole near the small antenna limit and they exhibit virtually identical radiation resistance properties at low frequencies. Finally, it is shown that the fractal limit in lowering of resonant frequency is related to the limit in the increase in the antenna's effective volume.

The resonant properties of several small planar space-filling fractal antennas are considered over a range of self-resonant frequencies. These space-filling antennas have differing geometries and total wire length, but occupy the same planar area. The resonant properties considered include radiation resistance, efficiency, and quality factor. It is demonstrated that the resonant properties of these antennas are essentially the same, independent of significant differences in antenna geometry and total wire length.

The effect of length bin width on growth estimation in integrated age-structured stock assessments

Stereospecific analysis of the major metabolites of ibuprofen in urine by sequential achiral-chiral high-performance liquid chromatography

In this paper, we present TQPF, a Timing-Driven Quadratic-based Placement Tool for FPGAs. Quadratic placement algorithms try to minimize total squared wire length by solving linear equations. The resulting placement tends to locate all cells near the center of the chip with a large amount of overlap. Also, since squared wire length is only an indirect measure of linear wire length, the resulting total wire length may not be minimized. We propose methods to alleviate the above two problems that give high-quality results while minimizing the total run time. We incorporate multiple iterations of equation-solving process together with a technique for pulling nodes out of the dense area while minimizing linear wire length. Experimental results using 20 Microelectronics Center of North Carolina (MCNC) benchmark circuits show that, on average, TQPF is approximately three times faster than the well-known Versatile Placement and Routing tool for FPGAs (VPR). The estimated total wire length, on average, is only 1.4% longer, and the critical path delay is 4.9% lower.

With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture (called Planar-CRX). Our Planar-CRX method integrates the extended deferred-merge embedding algorithm (DME-X, which extends the DME algorithm to X architecture) with modified Ohtsuki’s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.

Fretting wear studies were conducted on AZ91 and AE42 magnesium alloys against steel ball. Average coefficient of friction (COF) remains steady with the increase in running time. However, average coefficient of friction decreases with the increase in normal load and frequency and marginally increases with the increase in amplitude. A constant average coefficient of friction of 0.06 was observed for both AZ91 and AE42 under dry sliding conditions at normal load of 50 N. Wear volume increases linearly with increasing running time. Wear volume first decreases sharply, attains minima, and then increases marginally with the increase in normal load. However, wear volume increases with increasing amplitude and frequency. Higher specific wear rate of 10.5 × 10−6 mm3 N−1·m−1 was observed for AE42, as compared to 4.5 × 10−6 mm3 N−1·m−1 for AZ91. The wear in magnesium alloy was caused by a combination of adhesion, abrasion, oxidation, delamination, and plastic deformation under different fretting conditions.

We suggest an approach to optimize data mining in modern applications that work on distributed data. We formally transform a high-level functional representation of a data-mining algorithm into a parallel implementation that performs as much as possible computations locally at the data sources, rather than accumulating all data for processing at a central location as in the traditional MapReduce approach. Our approach avoids the main disadvantages of the state-of-the-art MapReduce frameworks in the context of distributed data: increased run time, high network traffic, and an unauthorized access to data. We use the popular data-mining algorithm – Naive Bayes – for illustrating our approach and evaluating it experimentally. Our experiments confirm that the implementation of Naive Bayes developed by using our approach significantly outperforms the traditional MapReduce-based implementation regarding the run time and the network traffic.