ARMINTEL: A Heterogeneous Microprocessor Architecture Enabling Intel Applications on ARM

The MIPS computer architecture is widely used in undergraduate computer architecture and organization courses because of its straightforward design. MIPS is the primary example of the popular textbook Computer Organization and Design [2], used at over 400 universities. We describe a GUI, Java-based simulator for the MIPS assembly language, with characteristics that emphasize usefulness to undergraduate computer science students and - importantly - their instructors.Java and Sun are trademarks or registered trademarks of Sun Microsystems, Inc. in the United States and other countries.

With the advent of the mobile industry, we face new security challenges. ARM architecture is deployed in most mobile phones, homeland security, IoT, autonomous cars and other industries, providing a hypervisor API (via virtualization extension technology). To research the applicability of this virtualization technology for security in this platform is an interesting endeavor. The hypervisor API is an addition available for some ARMv7-a and is available with any ARMv8-a processor. Some ARM platforms also offer TrustZone, which is a separate exception level designed for trusted computing. However, TrustZone may not be available to engineers as some vendors lock it. We present a method of applying a thin hypervisor technology as a generic security solution for the most common operating system on the ARM architecture. Furthermore, we discuss implementation alternatives and differences, especially in comparison with the Intel architecture and hypervisor with TrustZone approaches. We provide performance benchmarks for using hypervisors for reverse engineering protection.

The performance monitoring of computer systems is a complex affair, made even more challenging by the increasing gap between hardware and software. Methods that collect and feed data to performance analysis can usually be classified into one of two groups. Methods in the first group (e.g., software instrumentation), can be accurate but have unacceptable overheads and offer no insight into the interaction of the software and the hardware. Methods in the second group (e.g., hardware supported) run in real time and connect code to the response in the architecture, at a considerable decrease in accuracy, with a high degree of specificity to the hardware and therefore with limited actionable information made available. In this work, we focus on the latter group - the collection and analysis of raw performance data sourced from hardware Performance Monitoring Units, built into the majority of processors. The periodic collection of samples (Event Based Sampling), containing code locations, for instance, can be triggered on events such as retired instructions or cache misses. We quantify accuracy improvements to existing methods, propose a better performing method of performance data collection and a new architecture-agnostic method of performance data analysis. In our experiments, we analyze compiled, large-scale production workloads, industry standard benchmarks, and micro-benchmarks reproducing specific architectural behaviors. First, we focus on performance data collection methods and their accuracy, when establishing instruction retirement rates. These vary from least to most advanced and we examine the low level factors influencing accuracy. In particular, we employ a method based on Last Branch Records, a hardware facility present on some Intel architectures, which allows for the sampling of short records of last taken branches leading up to the sample. We compare the most commonly used method, its improved derivatives and the Last Branch Record based method. With respect to the first method, we observe accuracy improvements of up to 18x on synthetic benchmarks and 15x on real applications. Second, to further improve accuracy, we propose a new collection method named Hybrid Basic Block Profiling, fusing those based on Last Branch Records and the widely used Event Based Sampling. We apply simple machine learning techniques to determine the operating criteria. As a demonstration of capability, our method and a profiling tool are used to generate Instruction Mixes, which traditionally require good quality data at the most detailed level of granularity - basic blocks. Compared to software instrumentation, we observe an improvement in runtime of up to 76x, while keeping instruction attribution errors at 2.1% on average. In our third contribution we describe an architecture-agnostic performance analysis methodology called Hierarchical Cycle Accounting. The user is presented with a navigable hierarchy of microarchitectural issues, expressed in a metric that is universal and simple to compare - core cycles. We develop a reference implementation for the Intel Ivy Bridge microarchitecture and provide pointers for implementations on other processor architectures. Our approach and tool are successfully used by non-experts to improve and vectorize complex scientific code. Experts benefit as well - by being able to pinpoint software issues undetected by other methods, and identifying a bug in a family of Intel processors.

With the prevailing of smart devices (e.g., smart phone, routers, cameras), more and more programs are ported from traditional desktop platform to embedded hardware with ARM or MIPS architecture. While the compiled binary code differs significantly due to the variety of CPU architectures, these ported programs share the same code base of the desktop version. Thus it is feasible to utilize the program of commodity computer to help understand those cross-compiled binaries and locate functions with similar semantics. However, as instruction sets of different architectures are generally incomparable, it is difficult to conduct a static cross-architecture binary code similarity comparison. To address, we propose a semantic-based approach to fulfill this target. We dynamically extract the signature, which is composed of conditional operations behaviors as well as system call information, from binaries on different platforms with the same manner. Then the similarity of signatures is measured to help identify functions in ported programs. We have implemented the approach in MOCKINGBIRD, an automated analysis tool to compare code similarity between binaries across architectures. MOCKINGBIRD supports mainstream architectures and is able to analyze ELF executables on Linux platform. We have evaluated MOCKINGBIRD with a set of popular programs with cross-compiled versions. The results show our approach is not only effective for dealing with this new issue of cross-architecture binary code comparison, but also improves the accuracy of similarity based function identification due to the utilization of semantic information.

Fault Injection for Linux Device Drivers on x86, MIPS and ARM Architectures

This study thoroughly analyzes the cybersecurity status of Small Office/Home Office (SOHO) Wi-Fi routers. These routers are crucial but frequently overlooked elements in network infrastructure, particularly in light of the impact of the COVID-19 pandemic on network security. The pandemic has led to shifts in network usage patterns, blurring traditional security perimeters and extending them into private residences, creating additional points of vulnerability in urban environments. Our nationwide research evaluated an extensive dataset of router brands and models currently used at scale. We measured the prevalence of known vulnerabilities, assessed the currency of userspace and kernel software versions, and compared the security robustness of proprietary firmware against open-source alternatives. Our findings reveal a concerning landscape of widespread vulnerabilities and outdated software components, posing latent risks to end-users. The results indicate a predominance of Linux on MIPS and ARM architectures, with an average delay of 5 to 10 years between the release of the kernel and the implementation of the most recent firmware versions. As a result, we observed an average of 1344 and 72 vulnerabilities in the kernel and applications. One significant discovery from our research is that replacing the manufacturer's original firmware with open-source alternatives, such as DD-WRT, OpenWrt, and Tomato, can substantially enhance the security of the software stack. This enhancement results in improvements of up to 97% in the case of binaries and 98.42% in the kernel. Our research helps increase cybersecurity awareness by pinpointing critical home network environment weaknesses and alerting the need for more rigorous security practices in producing and maintaining SOHO routers. This investigation also allowed the report of a new remote code execution vulnerability (disclosed in CVE-2022-46552).

With the emergence of social networks and improvements in computational photography, billions of JPEG images are shared and viewed on a daily basis. Desktops, tablets and smartphones constitute the vast majority of hardware platforms used for displaying JPEG images. Despite the fact that these platforms are heterogeneous multicores, no approach exists yet that is capable of joining forces of a system's CPU and GPU for JPEG decoding.In this paper we introduce a novel JPEG decoding scheme for heterogeneous architectures consisting of a CPU and an OpenCL-programmable GPU. We employ an offline profiling step to determine the performance of a system's CPU and GPU with respect to JPEG decoding. For a given JPEG image, our performance model uses (1) the CPU and GPU performance characteristics, (2) the image entropy and (3) the width and height of the image to balance the JPEG decoding workload on the underlying hardware. Our runtime partitioning and scheduling scheme exploits task, data and pipeline parallelism by scheduling the non-parallelizable entropy decoding task on the CPU, whereas inverse cosine transformations (IDCTs), color conversions and upsampling are conducted on both the CPU and the GPU. Our kernels have been optimized for GPU memory hierarchies.We have implemented the proposed method in the context of the libjpeg-turbo library, which is an industrial-strength JPEG encoding and decoding engine. Libjpeg-turbo's hand-optimized SIMD routines for ARM and x86 architectures constitute a competitive yardstick for the comparison to the proposed approach. Retro-fitting our method with libjpeg-turbo provides insights on the software-engineering aspects of re-engineering legacy code for heterogeneous multicores.We have evaluated our approach for a total of 7194 JPEG images across three high- and middle-end CPU--GPU combinations. We achieve speedups of up to 4.2x over the SIMD-version of libjpeg-turbo, and speedups of up to 8.5x over its sequential code. Taking into account the non-parallelizable JPEG entropy decoding part, our approach achieves up to 95% of the theoretically attainable maximal speedup, with an average of 88%.

Recent research has shown that heterogeneous multicore architectures have the potential to further improve single thread performance. In such architectures different phases of the application are executed on different cores to improve performance and energy efficiency. However, restricting the cores to a single ISA limits the achievable performance gain. Different phases of applications also have shown affinity towards different ISAs due to their characteristics, functionality etc. Heterogeneous ISA architectures thus attempt to execute these different phases on their respective affine cores to fully harness ISA diversity. However, in such architectures, estimating the best migration point from one ISA to another, is an open research problem. This paper proposes a performance model for execution time estimation of heterogeneous ISAs which naturally extends to dynamic scheduling. The model is centred around execution time and a few on-line parameters. Regression techniques have been used to model the performance. Experimental evaluation shows that the proposed model has 78% accuracy in estimating migration from ARM ISA to X86 ISA.

Performance and energy consumption are well-known constraints of modern embedded systems, thus, application analysis in early stages of the development cycle is mandatory. However, the few available tools to evaluate the behaviour of an application considering different architectures are not able to provide a complete solution for this task. In this context, this work presents a multi-architecture profiling tool for Android applications, which fully supports ARM, MIPS, and x86 architectures. It provides a wide range of information per application, including energy consumption, execution time and other statistics. For that, we have extended the Android Emulator QEMU and developed post-processing tools. As case study, we have compared different architectures in terms of performance and energy consumption. By the use of the proposed tool, we show that, given a fixed energy budget, a different amount of applications can be executed depending on how they were implemented, which varies according to the processor.

Our forthcoming national experiment in increased health information technology (HIT) adoption funded by the American Recovery and Reinvestment Act of 2009 will require a comprehensive approach to evaluating HIT. The quality of evaluation studies of HIT to date reveals a need for broader evaluation frameworks that limits the generalizability of findings and the depth of lessons learned. Develop an informatics evaluation framework for health information technology (HIT) integrating components of health services research (HSR) evaluation and informatics evaluation to address identified shortcomings in available HIT evaluation frameworks. A systematic literature review updated and expanded the exhaustive review by Ammenwerth and deKeizer (AdK). From retained studies, criteria were elicited and organized into classes within a framework. The resulting Health Information Technology Research-based Evaluation Framework (HITREF) was used to guide clinician satisfaction survey construction, multi-dimensional analysis of data, and interpretation of findings in an evaluation of a vanguard community health care EHR. The updated review identified 128 electronic health record (EHR) evaluation studies and seven evaluation criteria not in AdK: EHR Selection/Development/Training; Patient Privacy Concerns; Unintended Consequences/ Benefits; Functionality; Patient Satisfaction with EHR; Barriers/Facilitators to Adoption; and Patient Satisfaction with Care. HITREF was used productively and was a complete evaluation framework which included all themes that emerged. We can recommend to future EHR evaluators that they consider adding a complete, research-based HIT evaluation framework, such as HITREF, to their evaluation tools suite to monitor HIT challenges as the federal government strives to increase HIT adoption.

Nowadays, large number of cloud-based techniques have been used in industrial control systems (ICS), which also brings many security threats. The emergence of security-aware industrial control has paved the way of security-aware scheduling in cloud-based industrial applications. Actually, most cloud-based industrial applications are time sensitive, which need real-time processing. Edge cloud computing paradigm extends the computing ability of traditional cloud model with low-latency local resources. Thus, heterogeneous clouds that consist of both centralized resources and edge resources may be a promising resource model to provide both scalable and low-latency resources for cloud-based industrial applications. In view of these challenges, in this article, we propose a security-aware dynamic scheduling method for real-time resource allocation in ICS. First, a three-level security model is designed for both tasks and cloud resources in ICS, and a two-tier heterogeneous cloud architecture is introduced. Accordingly, a security-aware scheduling method based on distributed particle swarm optimization is presented for resource allocation with security concerns. To deal with the dynamics of edge resources and the mobility of mobile industrial applications, a dynamic scheduling mechanism based on dynamic workflow model is proposed for real-time optimization. Experimental results validate that the scheduling control policy proposed in this article can achieve a good balance between scheduling performance and security performance.

At present, Google’s Android system has the characteristics of open source, rich software functions, and good user experience, and has been highly recognized by a wide range of applications and the market. If the Loongson platform wants to make a difference in mobile terminals and other fields, it needs to support the Android system. However, although the native Android system supports multiple architectures, it only performs a lot of optimizations for the ARM architecture. For other architectures, Google only provides a generic version. This brings a huge challenge to the Loongson processor based on the MIPS architecture. Based on the analysis of the Android system, this paper studies the Android transplantation method of the Loongson 2K1000 platform in detail realizes the transplantation of the Android Lollipop system on the platform and has passed the verification of the Loongson 2K1000 platform.

The traditional cost estimation process in construction involves extracting information from diverse data sources and relying on human intuition and judgment, making it time-intensive and error-prone. While recent advancements in large language models offer opportunities to automate these processes, their effectiveness in cost estimation tasks remains underexplored. Prior studies have investigated LLM applications in construction, but there is a lack of studies that have systematically evaluated their performance in cost estimation or proposed a framework for systematic evaluations of their performance in cost estimation and ways to enhance their accuracy and reliability through prompt engineering. This study evaluates the performance of pre-trained LLMs (GPT-4o, LLaMA 3.2, Gemini 2.0, and Claude 3.5 Sonnet) for conceptual cost estimation, comparing zero-shot prompting with a modular chain-of-thought framework. The results indicate that zero-shot prompting produced incomplete responses with an average confidence score of 1.91 (64%), whereas the CoT framework improved accuracy to 2.52 (84%) and achieved significant gains across BLEU, ROUGE-L, METEOR, content overlap, and semantic similarity metrics. The proposed modular CoT framework enhances structured reasoning, contextual alignment, and reliability in estimation workflows. This study contributes by developing a conceptual cost estimation framework for LLMs, benchmarking baseline model performance, and demonstrating how structured prompting improves estimation accuracy. This offers a scalable foundation for integrating AI into construction cost estimation workflows.

Electric power grids are undergoing a modernization process. By relying on the ICT infrastructure and on Internet connectivity, these so-called Smart Grids are now able to provide new functionalities and to become more efficient. However, despite the existence of a few standards that aim to specify the secure operation of Smart Grids, utility companies do not have a comprehensive set of metrics and evaluation tools for assessing security properties in these infrastructures. Thus, it is necessary to develop new toolsets to provide support for vulnerability analysis in Smart Grids. This paper proposes ASTORIA, a framework developed to allow the simulation of attacks and the evaluation of their impact on Smart Grid infrastructures, using closely-related real devices and real topologies comprising both power grid elements as well as ICT and networking equipment. We anticipate that ASTORIA can be used by Smart Grid operators not only to analyze the impact of malicious attacks and other security threats in different components, but also to permit the development and evaluation of anomaly detection techniques in a simulation environment. Further, we present evaluation scenarios illustrating customizable Smart Grid topologies, comprising sensors, master and remote stations, and using an extensible set of attack profiles.

This chapter presents the infrastructure for modeling intellectual property (IP). After a brief introduction to ARM IP and architecture, the modeling and simulation strategies are presented for the RISC CPUs and system-on-chips (SoCs) based on ARM IP. We will explain how the initial investigation of the processor architecture and microarchitecture for performance and power is accomplished before the real design phase. This will be followed by the discussion of different modeling techniques used in the processor design stage such as RTL simulation, emulation, and FPGA prototyping. Then, we will look into the system modeling/simulation frameworks from programmer’s and system designer’s perspectives and discuss their trade-offs. Finally, we will discuss the verification strategies for validating the processor design from ad hoc test techniques, random coverage strategies, assertion-based verification, and formal verification methods.