Asynchronous implementation of discrete event controllers based on safe automation Petri nets

Petri nets have been extensively applied for specification, design, verification, performance evaluation, and simulation of discrete event control systems (DECS). The usual way to verify the dynamic behaviour of DECS design is to employ a process-based model, which proves to be impractical in application because the process-based model does not usually fully correspond to the control programming behaviour. This paper proposes a sensor-based stage Petri net (SBSPN) to represent a programmable logic controller (PLC) stage logic diagram (LD) for discrete-event control design. The new technique is able to simplify the modelling process of the complex PLC program without considering the interlocking problem within the ladder diagram. An illustrated example is used to explore the new methodology. The proposed method contains the power and flexibility of the Petri net analysis prior to the PLC implementation. It is believed that this technique is significant for industry practice.

As automated manufacturing systems become more complex, the need for an effective design tool to produce both high-level discrete event control systems (DECS) and low-level implementations becomes more important. Petri nets represent the most effective method for both the design and implementation of DECSs. In this paper, automation Petri nets (APN) are introduced to provide a new method for the design and implementation of DECSs. The APN is particularly well suited to multiproduct systems and provides a more effective solution than Grafcet in this context. Since ordinary Petri nets do not deal with sensors and actuators of DECSs, the Petri net concepts are extended, by including actions and sensor readings as formal structures within the APN. Moreover, enabling and inhibitor arcs, which can enable or disable transitions through the use of leading-edge, falling-edge and level of markings, are also introduced. In this paper, the methodology is explained by considering a fundamental APN structure. The conversion of APNs into the IEC1131-3 ladder diagrams (LD) for implementation on a PLC is also explained by using the token passing logic (TPL) concept. Finally, an illustrative example of how APNs can be applied to a discrete manufacturing problem is described in detail.

This paper describes a flexible and systematic implementation method of Petri Nets that can be applied to high speed parallel control. This paper suggests a hard-wired implementation for a high frequency clock-driven system with little jitter. To implement Petri Nets with synchronous (clock-driven) digital circuits, a Synchronous Petri Net is proposed. The suggested implementation method is based on a regular cell-array such as FPGA (field programmable gate array). Radix-k Petri Net and Radix-k conversion are defined to solve technology mapping problem of FPGA that consists of k-size cells. Cell usage, cell utilization, cell complexity, and speed index are defined and derived, which are used for quantitative analysis and efficient design. To help the design process, necessary CAD tools such as design entry library, hard-macro library, and net-list converter are developed. The suggested method is demonstrated using Xilinx FPGA, and its operation is verified by computer simulations.

Motivated by the demand for Petri net software tools for control of discrete event systems,a Petri net-based discrete event simulation and control software tool is designed and developed.By analyzing the requirements of discrete event simulation and control,the main functions and objectives of the software tool are established.The architecture of software tool is designed accordingly.Subsequently,several key techniques for the software development are researched including proposing of control Petri nets together with design of their basic classes,save and read of Petri net models,Petri net-based simulation and control,and networked software construction in the Client/Server mode.Finally,the Petri net-based discrete event simulation and control software tool is developed,which not only possesses the functions of Petri net modeling and analysis,but also is capable of implementing Petri net-based control and simulation of discrete event systems through networks.Application result of the software tool on a reconfigurable machining system test-bed shows that the software tool is valid and practical.

In this paper a hybrid approach is proposed for supervisory control of discrete event systems (DES) subject to forbidden states. Assuming that an uncontrolled bounded Petri net (PN) model of a (plant) DES and a set of forbidden state specifications are given, the proposed approach computes a maximally permissive and nonblocking closed-loop hybrid model. The first step is to simplify the given PN model by means of PN reduction rules. The simplified model and the specifications are then represented as buffers, and supervisory control theory (SCT) is applied to obtain a Ramadge–Wonham (RW) supervisor in the form of an automaton. After reduction of the latter’s state size by a ‘control congruence’, the simplified RW supervisor is represented by a so-called auto-net and coupled to the given uncontrolled PN plant model by means of inhibitor arcs to represent the disabling actions. The plant model and supervisor auto-net run concurrently, synchronizing on shared events. This procedure provides a maximally permissive and nonblocking ‘hybrid’ (mixed PN/automaton) closed-loop controlled system. The method is straightforward logically, graphically, and technologically. Its applicability is shown by two examples, one of them a workcell from the PN control literature.

Petri nets have been extensively applied for specification, design, verification, performance evaluation, and simulation of discrete-event control systems. A real-time Petri net is a further improvement over the timed Petri net. The paper proposes to use a real-time Petri net to represent the stage programming of a programmable logic controller for a discrete-event control system. An illustrated example is used to explore the Petri net-based PLC stage programming methodology.

State-Partition-Based Control of Discrete Event Systems for Enforcement of Regular Language Specifications

The soft computing algorithms are being nowadays used for various multi input multi output complicated non linear control applications. This paper presented the development and implementation of back propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in programmable systems. For the neural network based instrument prototype in real time application. The conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGA have higher speed and smaller size for real time application than the VLSI design. The challenges are finding an architecture that minimizes the hardware cost, maximizing the performance, accuracy. The goal of this work is to realize the hardware implementation of neural network using FPGA. Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL)and is implemented in FPGA chip. MATLAB ANN programming and tools are used for training the ANN. The trained weights are stored in different RAM, and is implemented in FPGA. The design was tested on a FPGA demo board. Keywords- Backpropagation, field programmable gate array (FPGA) hardware implementation, multilayer perceptron, pressure sensor, Xilinx FPGA.

The effort in reducing the area of AES implementations has largely been focused on Application-Specific Integrated Circuits (ASICs) in which a tower field construction leads to a small design of the AES S-box. In contrast, a naive implementation of the AES S-box has been the status-quo on Field-Programmable Gate Arrays (FPGAs). A similar discrepancy holds for masking schemes – a wellknown side-channel analysis countermeasure – which are commonly optimized to achieve minimal area in ASICs.In this paper we demonstrate a representation of the AES S-box exploiting rotational symmetry which leads to a 50% reduction of the area footprint on FPGA devices. We present new AES implementations which improve on the state of the art and explore various trade-offs between area and latency. For instance, at the cost of increasing 4.5 times the latency, one of our design variants requires 25% less look-up tables (LUTs) than the smallest known AES on Xilinx FPGAs by Sasdrich and Guneysu at ASAP 2016. We further explore the protection of such implementations against first-order side-channel analysis attacks. Targeting the small area footprint on FPGAs, we introduce a heuristic-based algorithm to find a masking of a given function with d + 1 shares. Its application to our new construction of the AES S-box allows us to introduce the smallest masked AES implementation on Xilinx FPGAs, to-date.

We propose a formalism for decentralized control of discrete event systems with communications. The formalism is based on PN/sup 2/, a class of agent-oriented Petri nets proposed by the author (2001). The main difference between PN/sup 2/ and Petri nets is that each token, representing an agent, is also a Petri net. The decentralized control system to be modeled has the following features: (1) the system is asynchronous and has no global clock; (2) some events may occur concurrently; (3) the system is controlled by several control agents, each of which perceives only a subset of occurring events, and can control only a subset of events; and (4) each control agent can communicate with other agents. By communications, each agent can know occurrences of events that are not observable for it, and can ask other agents to disable events that are not controllable for it. Using the formalism, we define a problem concerning control synthesis.

Lightweight implementation of security primitives, e.g., physical unclonable functions (PUFs) and true random number generator, in field programmable gate array (FPGA) is crucial replacement of the conventional decryption key stored in battery-backed random access memory or E-Fuses for the protection of field reconfigurable assets. A slice is the smallest reconfigurable logic block in an Xilinx FPGA. The entropy exploitable from each slice of an FPGA is an important factor for the design of security primitives. Previous research has shown that the locations of slices can impact the quality of delay-based PUF designs implemented on FPGAs. To investigate the effect of the placement of each single-bit PUF cell free from the routing resource constraint between slices, single-bit ring oscillator (RO) and identity-based PUF design (Pi-coPUF) cells that can each be fully fitted into a single slice are evaluated. To accurately evaluate their statistical performance, data from a large number of devices are required. To this end, 217 Xilinx Artix-7 FPGAs has been employed to provide a large-scale comprehensive analysis for the two designs. This is the first time single-slice disorder-based security entities have been investigated and compared on 28-nm Xilinx FPGA. Uniqueness, uniformity, correlation, reliability, bit-aliasing and min-entropy of each type of cell are evaluated for four different types of cell placement. Our experimental results corroborate that the location of both cell types in the FPGA affects their performances. For both cell types, the lower the correlation between devices, the higher the min-entropy and uniqueness. Overall, the min-entropy, correlation and uniqueness of PicoPUF are slightly higher than those of RO. Otherwise, the uniformity, bit-aliasing and reliability of the PicoPUF are slightly lower than those of the RO. Comparing the resource usage and metrics of the PicoPUF, ring oscillator PUF and some existing memory-based PUF implementations, PicoPUF stands out as a lightweight FPGA-based weak PUF design. The raw data for the PicoPUF design are made publicly available to enable the research community to use them for benchmarking and/or validation.

Design of a Discrete Event Controller for a Model Railway

This paper explores the use of the Xilinx's system generator development tool for the implementation of control algorithms on Xilinx field programmable gate arrays (FPGA). The Simulink plug in complements traditional hardware description language (HDL) by providing a graphical language with a higher level of abstraction for the development of FPGA designs. After taking into consideration the challenges of converting control designs that have been implemented and verified within the Simulink environment to FPGA hardware implementation, a systematic approach is presented. As a case study, a FPGA implementation of a control system was derived and verified for a simulated unmanned ground vehicle (UGV). The design example demonstrates the validity of the presented method as an efficient and reliable method for rapid system prototyping for designs developed using the Simulink environment.

This study deals with the formal modeling and verification of reconfigurable discrete event control systems (RDECSs). The behavior of an RDECS is represented by that of control components (CCs) and the communication among them. A new formalism, called Reconfigurable Timed Net Condition/Event Systems (TNCES) (R-TNCES), is proposed for the optimal functional and temporal specification of RDECS, which is defined by a behavior module and a control module. The former is a union of various superposed TNCESs, where TNCES-based CC modules are basic units. The latter is a set of reconfiguration functions dealing with the automatic transformations of these TNCESs in response to errors or user requirements by enabling or disabling CC modules, changing condition signals and/or event signals among them, and also treating the state feasibility before and after reconfigurations. To control the verification complexity of R-TNCES, a layer-by-layer verification method is developed, where the similarities of different TNCESs in the behavior module are considered. The contribution of this original paper is applied to a benchmark production system.

Recently, many researches have investigated efficient reverse engineering methods to restore Programmable Logic Points (PLPs) and Programmable Interconnect Points (PIPs) in SRAM-based Field Programmable Gate Arrays (FPGAs). However, the research on the restoration of Programmable Content Points (PCPs) such as memory data are rarely studied. In this paper, we propose an efficient reverse engineering method to recover Read Only Memory (ROM) data, which is essential for the implementation of modern digital circuits. First, we analyze the FPGA hardware resources mapped to Xilinx primitive library of ROM, and next the proposed reverse engineering process is explained using mapping relation between ROM data and hardware resources. As an example, XC3S50 FPGA of Xilinx Sparatan-3 family is utilized, and the process of restoring the SBOX of AES (Advanced Encryption Standard) is provided as a practical application.