At-Speed Testing with Timing Exceptions and Constraints-Case Studies

Unit testing is an established practice in professional software development. However, in high-performance computing (HPC) with its scientific applications, it is not widely applied. Besides general problems regarding testing of scientific software, for many HPC applications the effort of creating small test cases with a consistent set of test data is high.We have created a tool called FortranTestGenerator, that significantly reduces the effort of creating unit tests for subroutines of an existing Fortran application. It is based on Capture & Replay (C&R), that is, it extracts data while running the original application and uses the extracted data as test input data. The tool automatically generates code for capturing the input data and a basic test driver which can be extended by the developer to an appropriate unit test. A static source code analysis is conducted, to reduce the number of captured variables. Code is generated based on flexibly customizable templates. Thus, both the capturing process and the unit tests can easily be integrated into an existing software ecosystem.Since most HPC applications use message passing for parallel processing, we also present an approach to extend our C&R model to MPI communication. This allows extraction of unit tests from massively parallel applications that can be run with a single process.

Dear SCPE Reader, We present a selection of papers which are extensions of papers presented at the 7-th International Symposium on Parallel and Distributed Computing, 1–5 July 2008, in Krakow, Poland. The motivation for publishing the selection in the SCPE Journal was, on the one hand, to present the flavour of the research reported at the conference and on the other hand to present some of the most relevant topics currently focused on the research on parallel and distributed computing in general. The selection contains only 6 papers out of about 60 presented at the conference, and thus, is far from covering all relevant topics represented at the ISPDC 2008. This is because not all of the invited authors were patient enough to accept a fairly long paper publishing process. Nevertheless, we hope that the presented papers will bring you closer to the research covered by the ISPDC conferences and will encourage you to participate in future ISPDC editions. The first paper ``The Impact of Workload Variability on Load Balancing Algorithms'' is by Marta Beltran and Antonio Guzman from King Juan Carlos University in Spain. It concerns an important topic of load balancing in cluster systems, namely adaptativity of the load balancing algorithms to changes of the workload in the system. Adequate accounting for additional load in the hosting system is of great relevance for correct optimization effects. The paper presents a thorough formal analysis of the workload variability metrics and their influence on the quality of load balancing algorithms. Four basic activities appearing in load balancing algorithms are identified, and based on them some algorithmic solutions are proposed to correctly deal with workload variability in system load balancing. The problem of dynamic load balancing algorithms robustness has been discussed. Two different robustness metrics sensitive to the applied type of opimization: local task-oriented or a global one enable selecting task remote execution or migration as load balancing operations. The proposed approach is illustrated with experiments. The second paper ``Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems'' is by Abdoulaye Gamatie, Eric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser, from University of Lille and INRIA in France. The paper is concerned with a very advanced methodology of designing correct parallel embedded systems for intensive data-parallel computing. In their previous research, the authors of the paper designed the GASPARD embedded system design framework. It is based on the hardware/software co-design approach through model-driven engineering. The framework is based on an UML-like model specification language in which hardware and software elements are modelled using a component approach with special mechanisms for repetitive structures. This paper tries to combine the modelling framework of GASPARD with the mechanisms of synchronous languages to achieve design verifiability provided for such languages. The paper shows how GASPARD models can be translated into synchronous models based on data flow equations in order to formally check their correctness. The proposed approach is illustrated with an example of a video processing system. The third paper ``Relations Between Several Parallel Computational Models'' is by Stephan Bruda and Yuanqiao Zhang from Bishop’s University in Canada. The paper is concerned with theoretical aspects of shared memory systems described by the parallel random access machine PRAM model and aims in studying performance properties of different types of PRAM systems. The attention is focussed on analysing the computational power of two more sophisticated PRAM models (Combining CRCW and Broadcast Selective Reduction), which include data reduction in case of concurrent writes. The paper shows that these two models have equivalent computational power, which is a new result comparing the existing literature. The performance of both models applied to reconfigurable multiple bus machines was studied as a possible architectural solution for current VLSI processor implementations. It was shown that in such systems under reasonable assumptions concurrent-write does not enhance performance comparing the exclusive-write model. Another result important for the VLSI technology is that the Combining CRCW PRAM model (in which data of concurrent writes are arthmetically or logically combined before write) and the exclusive-write on directed reconfigurable busses perform in equivalent way under strong real-time requirements. The fourth paper ``Experiences with Mesh-Like Computations Using Prediction Binary Trees'' is by Gennaro Cordasco, Biagio Cosenza, Rosario de Chiara, Ugo Erra and Vittorio Scarano from the University ``degli Studi'' of Salerno and the University ``degli Studi della Biasilicata'' of Potenza in Italy. The paper concerns optimization methods for mesh-like computations in clusters of processors. The computations are perfomed assuming a phase-like program execution control using a tiling approach which reduces inter-processor communication. A temporal coherence is also assumed, which means that task sizes provide similar execution times in consecutive phases. Temporary coherent computations are structured in a Prediction Binary Tree, in which leaves represent computing tiles to be mapped to processors. A phase-by-phase semi-static load balancing is introduced to the scheduling algorithm. The scheduling algorithm is equipped with a predictor, which estimates the computation time of next phase tiles based on previous execution times and modifies the tiles to achieve balanced execution in phases. For this, two heuristics are used to leverage on data locality in processors. The proposed approach is illustrated by the example of interactive rendering with Parallel Ray Tracing algorithm. The fifth paper ``The Influence of the IBM pSeries Servers Virtualization Mechanism on Dynamic Resource Allocation in AIX 5L'' is by Maciej Mlynski from ASpartner Limited in Poland. The paper concerns a very up-to-date problem of system virtualization and presents the results of research carried on IBM pSeries servers. IBM is strongly developing the virtualization technique especially on IBM pSeries servers enabling an improved and flexible sharing of system resources between applications. The paper investigates novel facilities for dynamic resource management such as micro-partitioning and partition load manager. They enable dynamic creation of workload logical partitions of system resources and their dynamic mangement. It includes run-time resource re-alocation between logical partitions including setting of sharing specifications as well as run-time adding/removing/setting parameters of resources in the system. It remains an open question how to properly tune parameters of the operating system using the provided virtualization facilities to obtain the best efficiency for a given application program. The paper presents the results of experiments which study the effects of tuning the disk subsystem parameters under the IBM AIX 5L operating system with the use of the provided virtualization facilities on the resulting application execution performance. The results show that even small deterioration in the resource pool status requires an immediate adaptation of the operating system parameters to maintain the required performance. The sixth paper ``HeteroPBLAS: A Set of Parallel Basic Linear Algebra Subprograms Optimized for Heterogeneous Computational Clusters'' is by Ravi Reddy, Alexey Lastovetsky and Pedro Alonso from University College Dublin in Ireland and Polytechnic University of Valencia in Spain. The paper concerns the methodology for parallelization of linear algebra computations for execution in heterogeneous cluster environments. The design of the HeteroPBLAS library (Parallel Basic Linear Algebra Subprograms) for heterogeneous computational clusters is presented. The main contribution of the paper is the automation of the parallelization and optimization of the PBLAS, which is done by means of a special user interface and the underlying set of functions. An important element is here a performance model that is based on program code instrumentation, which determines parameters of the application and the executive heterogeneous platform relevant for execution performance of parallel code. The parameter values specified for or returned by execution of the performance model functions are next used for generation and optimal mapping of the parallel code of the library subroutines. The proposed approach is illustrated by experimental results of execution of optimized HeteroPBLAS programs on homogeneous and heterogeneous computing clusters. Marek Tudruj

Test case generation, selection and coverage from natural language

In this thesis, concepts for developing Spatial Data Infrastructures with an emphasis on visualizing 3D landscape and city models in distributed environments are discussed. Spatial Data Infrastructures are important for public authorities in order to perform tasks on a daily basis, and serve as research topic in geo-informatics. Joint initiatives at national and international level exist for harmonizing procedures and technologies. Interoperability is an important aspect in this context - as enabling technology for sharing, distributing, and connecting geospatial data and services. The Open Geospatial Consortium is the main driver for developing international standards in this sector and includes government agencies, universities and private companies in a consensus process. 
\n3D city models are becoming increasingly popular not only in desktop Virtual Reality applications but also for being used in professional purposes by public authorities. Spatial Data Infrastructures focus so far on the storage and exchange of 3D building and elevation data. For efficient streaming and visualization of spatial 3D data in distributed network environments such as the internet, concepts from the area of real time 3D Computer Graphics must be applied and combined with Geographic Information Systems (GIS). For example, scene graph data structures are commonly used for creating complex and dynamic 3D environments for computer games and Virtual Reality applications, but have not been introduced in GIS so far. 
\nIn this thesis, several aspects of how to create interoperable and service-based environments for 3D spatial data are addressed. These aspects are covered by publications in journals and conference proceedings. The introductory chapter provides a logic succession from geometrical operations for processing raw data, to data integration patterns, to system designs of single components, to service interface descriptions and workflows, and finally to an architecture of a complete distributed service network.
\nDigital Elevation Models are very important in 3D geo-visualization systems. Data structures, methods and processes are described for making them available in service based infrastructures. A specific mesh reduction method is used for generating lower levels of detail from very large point data sets. An integration technique is presented that allows the combination with 2D GIS data such as roads and land use areas. This approach allows using another optimization technique that greatly improves the usability for immersive 3D applications such as pedestrian navigation: flattening road and water surfaces. It is a geometric operation, which uses data structures and algorithms found in numerical simulation software implementing Finite Element Methods. 
\n3D Routing is presented as a typical application scenario for detailed 3D city models. Specific problems such as bridges, overpasses and multilevel networks are addressed and possible solutions described. The integration of routing capabilities in service infrastructures can be accomplished with standards of the Open Geospatial Consortium. An additional service is described for creating 3D networks and for generating 3D routes on the fly. Visualization of indoor routes requires different representation techniques.
\nAs server interface for providing access to all 3D data, the Web 3D Service has been used and further developed. Integrating and handling scene graph data is described in order to create rich virtual environments. Coordinate transformations of scene graphs are described in detail, which is an important aspect for ensuring interoperability between systems using different spatial reference systems. The Web 3D Service plays a central part in nearly all experiments that have been carried out. It does not only provide the means for interactive web-visualizations, but also for performing further analyses, accessing detailed feature information, and for automatic content discovery.
\nOpenStreetMap and other worldwide available datasets are used for developing a complete architecture demonstrating the scalability of 3D Spatial Data Infrastructures. Its suitability for creating 3D city models is analyzed, according to requirements set by international standards. A full virtual globe system has been developed based on OpenStreetMap including data processing, database storage, web streaming and a visualization client.
\nResults are discussed and compared to similar approaches within geo-informatics research, clarifying in which application scenarios and under which requirements the approaches in this thesis can be applied.
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Mining people's semantic trajectory behaviours from geotagged photographs

This research has first established that it is based on multiple methodologies developed to tackle the areas of engineering cargo handling systems, both at port and on-board vessels, as well as in the area of organisational self-assessment. It continued in reviewing the current status and future aspects of marine safety assessment together with an examination of a few major accidents. The major problems identified in marine safety assessment in this research are associated with inappropriate treatment of uncertainty in data and human error issues during the risk modelling estimation process and the calculation of failure probabilities. Following the identification of the research needs, this thesis has developed several analytical models for the safety assessment of cargo handling systems and organisational assessment structure. Such models can be effectively integrated into a risk-based framework using the marine formal safety assessment, safety case concepts. Bayesian network (BN) and evidential reasoning (ER) approaches applicable to cargo handling engineering systems have been proposed for systematically and effectively addressing uncertainty due to randomness and vagueness in data respectively. ER test cases for both a vessel selection process and a comparison of the safety maturity of different organisations in terms of self-assessment have been produced within a domain in which main and sub criteria have been developed for assessment reasons a long with the combination of the proposed model with existing organisational models. BN test case for a Liquefied Petroleum Gas (LPG) reliquefaction plant has been produced within a cause-effect domain in which Bayes' theorem is the focal mechanism of inference processing. A methodology aiming in finding the probability of failure when having variables ruled by uncertainty is established using certain variable transformation methods through the First and Second order reliability methodologies. Form/Sorm produces a most likely failure point, which is demonstrated through the application at a port cargo handling crane system. The outcomes have the potential to facilitate the decision-making process in a risk-based framework. Finally, the results of the research are summarised and areas where further research is required to improve the developed methodologies are outlined.

Interacting with the Web of Things

The paper concerns automatic generation of usage models from real-time software UML models. Firstly, we define the reasonably constrained real-time software UML artifacts, which include use case diagrams, timed sequence diagrams and the execution probability of each sequence diagram in its associated use case. Secondly, the paper presents a method that derives the software usage model from the constrained UML artifacts. The method elicits the messages associated with the objects under testing and their occurrence probabilities to generate the usage model of each use case. Timing constraints in sequence diagrams are considered during usage model generation. Then the usage models of use cases are integrated into the software usage model by utilizing the execution sequence relations between use cases. The usage models can be used to generate real-time software statistical test cases and facilitate real-time software statistical testing.

The present dissertation deals with the application of an adaptive mesh hp-refinement method to the time-dependent compressible Euler equations describing the flow of an inviscid fluid. The physical simulation space is a two-dimensional channel with bump through which an ideal gas flows. A big advantage of the Euler equations is the applicability to different Mach regimes. Thus, smooth solutions and those containing discontinuities can be simulated. As the underlying numerical technique, a pseudo-spectral element method using least squares is used. The grid consists of rectangles that have to be transformed into curved deformed elements in the area of the bump. The h-refinement is realized by means of a quadtree and the p-refinement by means of a stepwise increase of the polynomial degree by 2, whereby hanging nodes can arise. Compared to previous research, the Euler equations are examined with respect to four different refinement criteria in combination with the hp-adaptive pseudo-spectral element method. The refinement criteria are the gradient criterion, two spectral criteria and an edge detection method. For a first determination of the suitability of the criteria for the h-refinement and for a validation of the pseudo-spectral element method, these are used for the solution of three steady state convection equations for which the exact solutions are known. Finally, the full method is applied to three test problems for the Euler equations. The flow through the channel is realized by a smooth subsonic flow, a transonic flow with a shock, and a supersonic flow that contains reflective shocks. Since no analytical solution is known, we compare our results to other works that consider stationary grids for these test cases. It turns out that the applied adaptive method refines the grid in the regions of the stagnation points and those that have discontinuities. Thus prior knowledge about the location of the problem areas is not necessary. A smaller number of elements and locally higher polynomial degrees reduce the sizes of the systems of equations to be solved.

Researchers have proposed different methods for testing digital systems and circuits in the last couple of decades. The need for testing digital logic circuits has become more important than ever due to the growing complexity of such systems. During the design phase, testing is focusing on design defects, as well as manufacturing and wear out type of defects. Failures in digital systems could be caused, for example, by design errors, the use of inherently probabilistic devices, and manufacturing variability. As a way to test digital systems in a more efficient way, automated test generation has been proposed to automatically create tests that can quickly and accurately identify faulty components. Examples of such techniques are the sequential test generation, the scan path testing, and the random test generation techniques. With the research domain becoming more mature and growing, it is essential to systematically identify, analyze, and classify these contributions. We performed a systematic mapping study of automated test generation for digital circuits aimed at providing an overview of the application of these techniques. We focused on three of the most widely-used and well-supported hardware description languages (HDLs) for digital systems: Verilog, SystemVerilog, and VHDL. Our results suggest that the majority of the test generation methods for digital circuits are focused on the behavioral and register-transfer design levels. Fault-independent and fault-oriented test generation are the most frequently reported types of test generation methods, while HDL model simulation is the most common test generation technology used to search for test cases in these academic studies. While the results are suggesting a growing interest in this area, the majority of articles are published as conferences papers. Our results show that only 31% of the methods are implemented as software tools and only 63% of all contributions are actually generating executable test cases. This study makes three important contributions, (i) a state-of-the-art of test generation for digital system designs research is provided, (ii) the reported characteristics are identified in both the primary papers and experimental reports, (iii) gaps and opportunities for future test generation for digital system designs research are identified.

Background: Mitochondrial disorders are the most common congenital metabolic diseases. They are due to dysfunction of the mitochondria, the organelles that are responsible for energy (adenosine triphosphate) generation through the respiratory chain. Mitochondria are present in almost every body cells, therefore, their disorders cause various manifestations including encephalomyopathy, cardiomyopathy, and gastrointestinal symptoms. About 25% of mitochondrial disorders are secondary to mitochondrial DNA (mtDNA) genes mutations, and 75% are due to mutations in genes encoded in the nucleus (nuclear DNA or nDNA). Mitochondrial respiratory chain has five major complexes. Defect of each component can cause different clinical and imaging manifestations. Isolated complex I deficiency (OMIM: 252010) is the most common defect of respiratory chain in pediatrics. Complex I (NADH:ubiquinone oxidoreductase) is the largest component of the respiratory chain. It has 38 core subunits encoded by nDNA, and 7 core subunits encoded by mtDNA. Mutations of 17 nDNA genes (NDUFS1−4 and 6−8; NDUFA1, 2, 10, 11; NDUFB3, 9, 11; NDUFV1, 2; NDUFAF3; FOXRED1; ACAD9; MTFMT), and 7 mtDNA genes (MTND1−6; MTTS2) have been reported to cause complex I deficiency. Objectives: To investigate the neuroimaging patterns of pediatric mitochondrial respiratory chain complex I deficiency based on the affected gene. Methods: 16 genetically proven pediatric patients with complex I deficiency were found through searching the database of a genetics center and a pediatric neurology referral hospital. Of the included cases, conventional MRI of 14 patients were retrieved by calling the parents. The MR images were reviewed and reported by an expert radiologist blinded to the genetics results. The neuroimaging pattern of each gene mutation was determined by genotype-MRI correlation. Mann-Whitney U test and Fisher’s exact test were used for analyses. Results: Of 14 investigated patients, eight patients had nDNA genes mutation (NDUFS1 in four cases, NDUFS4 in two cases, NDUFA1 in one case, and NDUFV2 in one case) and six cases revealed mtDNA genes mutation (MTND3 in four cases, MTND4 in one case, and MTND6 in one case). 11 patients (78%) were male, and the rest were female. The mean age of the patients at the time of brain imaging was 3.1 years (range, 6 months−11 years). The mean age of the patients with nDNA mutations was significantly lower compared to the patients with mtDNA mutations (1.4 versus 5.3 years, p =0.03). Symmetrical brainstem lesions were present in all of the patients. Involvement of the basal ganglia was observed in 5/8 patients with nDNA and 5/6 cases of mtDNA mutations (p =0.58). Progressive cavitating leukoencephalopathy (periventricular and centrum semiovale white matter cavitary lesions with a rim of hyperintensity and subcortical sparing) was observed in three patients, all of whom had NDUFS1 mutation. All of these three patients revealed corpus callosal lesions. Corpus callosal involvement was absent in the rest of cases. Cortical hyperintensities were seen in 3/6 cases of mtDNA mutations (all with MTND3 mutation). Supratentorial cerebral atrophy was observed in 1/6 case of mtDNA mutation. Cerebellar signal abnormalities were present in 3/8 patients with nDNA and 3/6 cases of mtDNA mutations (p =1.00). Cerebellar atrophy was observed in 4/6 cases of mtDNA mutations (three cases with MTND3 and one case with MTND6 mutations), but none of nDNA mutations (p =0.01). Conclusions: In summary, neuroimaging abnormalities are manifested earlier in nDNA compared to mtDNA mutations. Brainstem involvement is a constant feature of complex I deficiencies. Cavitating leukoencephalopathy is highly suggestive of NDUFS1 mutation. Cortical signal abnormalities and cerebellar atrophy are present in mtDNA, but not nDNA, mutations. MRI pattern recognition can aid the physician and the geneticist to focus on a specific set of genes as the main cause of symptoms in a child.

The Yosida methods for incompressible viscous flows are investigated numerically in the aspect of local and global errors of volume conservation. Unsteady Stokes and Navier–Stokes flows past an obstacle inserted into 2D channel are used as the test cases. Open boundary conditions are imposed at the channel’s inlet and outlet. The results obtained by the Yosida-based Spectral Element Method (SEM) solvers are compared to the results obtained by the SEM solver using exact factorization of the Uzawa system. Analysis of parametric variation of the velocity divergence and the flow rate errors is presented. It is concluded that switching to higher-order Uzawa methods reduces substantially volume conservation errors and removes numerical artifacts observed at the channel’s inlet when the basic Yosida method is used.

Recently, large language models (LLMs) have shown great promise in automating unit test generation, significantly reducing the manual effort required by developers. To effectively evaluate the capabilities of LLMs in this domain, it is crucial to have a well-designed benchmark that accurately reflects real-world scenarios and mitigates common pitfalls. Existing LLM test generation benchmarks are limited by two critical drawbacks: data contamination and structurally simple function code. As a result, scientific conclusions drawn from empirical studies using these benchmarks may be compromised. The evidence presented may be biased due to contamination and may fail to generalize beyond toy programs due to structural simplicity. To address these problems, we introduce ULT (UnLeakedTestbench), a new benchmark specifically designed for function-level unit test generation from real-world Python functions. ULT is constructed through a multi-stage curation process that ensures high cyclomatic complexity and mitigates test case contamination. With 3,909 carefully selected function-level tasks, ULT provides a more realistic and challenging evaluation of LLMs’ test generation capabilities. We also provide PLT (PreLeakedTestbench), a pair benchmark of ULT with leaked tests designed to enable a controlled analysis of memorization versus reasoning in test generation. Based on the two datasets, we conduct a large-scale empirical study involving 12 state-of-the-art LLMs, comparing their performance against established benchmarks. Our evaluation results demonstrate that ULT is significantly more challenging. For example, test cases generated by LLMs only achieve 41.32%, 45.10%, 30.22%, and 40.21% for accuracy, statement coverage, branch coverage, and mutation score on average for all LLMs, respectively. These results are substantially lower than the corresponding metrics on TestEval (91.79%, 92.18%, 82.04%, and 49.69%) and PLT (47.07%, 55.13%, 40.07%, and 50.80%). In addition, different from existing benchmarks, ULT shows a strong correlation between test generation performance and code generation performance. For example, the correlation coefficient between the coding ability and test generation performance ( \(Pass@1\) ) on ULT is 0.79 (p = 0.002), while it is only 0.56 (p = 0.059) and 0.52 (p = 0.080) on TestEval and PLT, respectively. This indicates that ULT more effectively measures the generalization ability of LLMs. We also make ULT and evaluation results publicly available to foster further research 1 . ULT is available at https://github.com/huangd1999/UnLeakedTestBench .

The benefits of the continued progress in integrated circuit manufacturing have been numerous, most notably in the explosion of computing power in devices ranging from cell phones to cars. Key to this success has been strategies to identify, manage, and mitigate yield loss. One such strategy is the use of test structures to identify sources of yield loss early in the development of a new manufacturing process. However, the aggressive scaling of feature dimensions, the integration of new materials, and the increase in structural complexity in modern technologies has challenged the capabilities of conventional test structures. To help address these challenges, a new logic test chip, called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), has been developed. The CM-LCV utilizes a two- dimensional array of functional unit blocks (FUBs) that each implement an innovative functionality. Properties including fault coverage, logical and physical design features, and fault distinguishability are shown to be composable within the FUB array; that is, they exist regardless of the size and composition of the FUB array. A synthesis ow that leverages this composability to adapt the FUB array to a wide range of test chip design requirements is presented. The connection between the innovative FUB functionality and orthogonal Latin squares is identified and used to analyze the universe of possible FUB functions. Two additional variants to the FUB array are also developed: heterogenous FUB arrays utilize multiple FUB functions to improve the synthesis ow performance, while pipelined FUB arrays incorporate sequential circuit elements (e.g., ip- ops and latches) that are absent from the original combinational FUB array. In addition to the design of the CM-LCV, methods for testing it are presented. Techniques to create minimal sets of test patterns that exhaustively exercise each FUB within the FUB array are developed. Additional constraints are described for the heterogenous and pipelined FUB arrays that allow these techniques to be applied for both variant FUB arrays. Furthermore, a simple built-in self test (BIST) scheme is described and applied to a reference design, resulting in a 88.0% reduction in the number of test cycles required without loss in fault coverage. A hierarchical FUB array diagnosis methodology (HFAD) is also presented for the CM- LCV that leverages its unique properties to improve performance for multiple defects. Experiments demonstrate that this HFAD methodology is capable of perfect accuracy in 93.1% of simulations with two injected faults, an improvement on the state-of-the-art commercial diagnosis. Additionally, silicon fail data was collected from a CM-LCV manufactured using a 14nm process by an industry partner. A comparison of the diagnosis results for the 1,375 fail logs examined shows that the HFAD methodology discovers additional defects during multiple defect diagnosis that the commercial tool misses for 40 of the diagnosed fail logs. Examination of these cases shows that the additional defects found by the HFAD methodology can result in improved diagnosis confidence and more precise descriptions of the defect behavior(s). The contributions of this dissertation can thus be summarized as the description of the design, test, and diagnosis of a new logic test chip for use in yield learning during process development. This CM-LCV can be adapted to meet a wide range of test chip requirements, can be efficiently and rigorously tested, and exhibits properties that can be used to improve diagnosis outcomes. All of these claims are validated through both simulated experiments and silicon data.

This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.