Atomic-Scale Defects Associated with the Negative Bias Temperature Instability

Negative Bias Temperature Instability (NBTI) is a serious reliability issue for pMOS transistors. Normally, degradation due to NBTI is modeled based on test structure data or ring oscillators embedded within product die. In this paper, we present a new method to determine the NBTI model parameters through I/O circuit measurements. We determine a relationship between Δ V th and signature signal degradation and fit a model to the simulation results. The signature signal involves the calculation of the degradation in the voltage signature, measured as delay and amplitude shifts. Given an estimate of Δ V th we find NBTI model parameters. Then, using the NBTI parameters at test conditions, we scale to use conditions and calculate lifetime. The methodology enables the extraction of NBTI model parameters for individual chips, not just for the manufacturing process, and hence it becomes possible to identify chips that are more vulnerable to NBTI.

Both negative bias temperature instability (NBTI) and time dependent dielectric breakdown (TDDB) are two major reliability issues for long term performance of high-k gate stacks. In this work, these two degradation mechanisms were extensively analyzed to explore any possible correlation in terms of defects formation. A variety of dielectric stacks were considered to perform NBTI and TDDB. It was observed that NBTI induced defects, generated at the interface and in the interfacial layer were somewhat identical to the defects that dominate the breakdown process.

Negative Bias Temperature Instability (NBTI) is one of the dominant factors determining a device lifetime. NBTI causes a threshold voltage shift on a PMOS transistor. Modern LSI often has large on-chip SRAMs such as cache memories. NBTI affects the SRAM cell as degradation in Static Noise Margin (SNM), which is a measure of the read stability of the cell. Hence, a special technique for mitigating NBTI on on-chip SRAMs is required. We investigate features of NBTI via detailed simulations and find that a stress probability and a stress-recovery cycle are important parameters for mitigating it. These parameters are dependent upon the values stored in the cell and the value is dependent upon the on-chip memory configurations and applications. This paper presents the relationship among NBTI degradation, memory configurations, and target applications by focusing on the values stored in SRAM cells. Furthermore, these observations lead us to discuss guidelines for mitigating NBTI degradation of on-chip SRAMs.

To assess the impact of strain on negative bias temperature instability (NBTI), systematic studies were performed on devices with polycrystalline-Si/SiON as well as deposited metal gate/high-kappa and FUSI/high-kappa gate stacks. The effects of compressive stress, which acts as performance booster for PMOS devices, were studied, with strain introduced by stressor layers as well as SiGe source/drain techniques. Care was taken to account for side effects of processing steps used to introduce the strain, such as changes on threshold voltage or capacitance equivalent thicknesses, in order to obtain a fair evaluation of the intrinsic effect of strain on NBTI. NBTI measurements were complemented by charge pumping and noise measurements to obtain a comprehensive understanding of defects present and of their generation under stress. In addition, nanobeam diffraction strain measurements, as well as curvature mass simulations, were performed in order to investigate the impact of strain on carrier mobility in the vertical direction. Our studies showed consistently that there is no significant degradation of intrinsic NBTI behavior due to process-induced strain.

This paper examines the atomic-scale defects involved in a metal-oxide-silicon field-effect-transistor reliability problem called the negative-bias temperature instability (NBTI). NBTI has become the most important reliability problem in modern complementary-metal-oxide-silicon technology. Despite 40 years of research, the defects involved in this instability were undetermined prior to this paper. We combine DC gate-controlled diode measurements of interface-state density with two very sensitive electrically detected magnetic-resonance measurements called spin-dependent recombination (SDR) and spin-dependent tunneling (SDT). An analysis of these measurements provides an identification of the dominating atomic-scale defects involved in NBTI in pure- and plasma-nitrided oxide (PNO)-based devices. We are also able to observe atomic-scale defects involved in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based devices (although a definitive identification of the dominating defects structure was not possible). Our results in pure- devices indicate an NBTI mechanism which is dominated by the generation of P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b0</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b1</sub> interface-state defects. (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b0</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b1</sub> are both silicon dangling-bond defects, in which the central silicon is back-bonded to three other silicon atoms precisely at the interface). This observation is consistent with what most NBTI researchers have assumed. However, our observations in PNO devices contradict with what most NBTI researchers had previously assumed. We demonstrate that the dominating NBTI-induced defect in the plasma-nitrided devices is fundamentally different than those observed in pure-based devices. Our measurements indicate that the new plasma-nitrided NBTI-induced defect's physical location extends into the gate dielectric. The defect participates in both SDR and SDT. Our SDR results strongly indicate that the plasma-nitrided defect has a density of states which is more narrowly peaked than that of centers and is near the middle of the band gap. The high sensitivity of our SDT measurements allow an identification of the physical and chemical nature of this defect through observations of hyperfine interactions. The defects are silicon dangling bonds, in which the central silicon is back-bonded to nitrogen atoms. We call these NBTI-induced defects centers because of the similarities to the centers observed in silicon nitride (the silicon-nitrided center is also a silicon dangling bond in which the silicon atom is back-bonded to nitrogen atoms). The defect identification in plasma-nitrided devices helps to explain the following phenomena: (1) NBTI's enhancement in plasma-nitrided devices; (2) conflicting reports of NBTI-induced interface states and/or bulk traps; and (3) fluorine's ineffectiveness in reducing NBTI in plasma-nitrided devices. We also observe the atomic-scale defects involved in NBTI in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based devices and find that short- and long-term stressing generates different defects and that these defects are different than those observed in the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and plasma-nitrided devices. Our results also suggest that the NBTI-induced defects in these devices are physically located in the interfacial layer (not at the interface).

The tremendous scaling of the semiconductor devices is producing the high-density integrated circuits (ICs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) are the basic building blocks for the ICs. The lower area requirement with increased numbers of devices on a substrate makes it an interesting field of very-large-scale integration (VLSI) design. The reliability of the logic circuits is the concern issue in modern-era electronics. Reliability affects the overall performance of the logic circuits and possibility to the failure of the semiconductor devices. Negative bias temperature instability (NBTI) degradation is the major concern in ultra-deep submicron (DSM) regime. The negative threshold voltage of PMOS device when shifted in NBTI effect causes performance degradation over the time. NBTI degradation is the aging effect for PMOS device. This chapter presents the overview of NBTI effect and its possible solution.

Negative bias temperature instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, the effect of NBTI has rapidly grown in prominence, forcing designers to resort to a pessimistic design style using guard-banding. Since NBTI is strongly dependent on the time for which the PMOS device is stressed, different gates in a combinational circuit experience varying extents of delay degradation. This has necessitated a mechanism of quantizing the gate-delay degradation, to pave the way for improved design strategies. Our work addresses this issue by providing a procedure for determining the amount of delay degradation of a circuit due to NBTI. An analytical model for NBTI is derived using the framework of the reaction-diffusion model, and a mathematical proof for the widely observed phenomenon of frequency independence is provided. Simulations on ISCAS benchmarks under a 70nm technology show that NBTI causes a delay degradation of about 8% in combinational logic based circuits after 10 years (ap 3 times 108s)

In this paper, we investigated the effect of Negative Bias Temperature Instability (NBTI) in FinFET devices. For the simulation studies, we used the two-stage model - an NBTI model, which describes accurately the behaviour of devices during stress and relax phase of NBTI. The effect of stress bias, initial concentration of oxygen vacancy precursors and temperature on NBTI degradation in FinFETs are analysed.

Gate dielectric traps are becoming a major concern in the high-k/metal gate devices. In this paper, new experimental results and in-depth study on gate current random telegraph signal (Ig RTS) noise in SiON/HfO2/TaN gate stack p-type metal–oxide–semiconductor field-effect transistors (PMOSFETs) are reported. Single carrier trapping/detrapping in the high-k/metal gate stack under negative bias temperature instability (NBTI) stress is observed for the first time. The location of traps, the impacts of gate bias, temperature and substrate bias are discussed for understanding the RTS mechanism in high-k devices. Moreover, during long time stress, an abrupt change of amplitude of Ig fluctuation and the mean capture and emission time is also observed for the first time, due to new trap generated or activated by the NBTI degradation. The characteristics of the single carrier trapping/detrapping behavior under NBTI stress are very different from that on the normal bias condition, which give us more information about the traps in the high-k/metal gate stack.

We report a broad study of Negative Bias Temperature Instability (NBTI) in Replacement Metal Gate (RMG) SiGe core FinFETs, focusing on the impact of Ge concentration, fin width, fin side-wall orientation, and interface passivation by high pressure anneals (HPA). We focus on Si-cap-free gate stacks, which offer simplified FinFET integration. Direct oxidation of SiGe yields poor interface quality, which can be restored by HPA. Despite a wide distribution of defect levels in the interfacial layer due to Ge suboxide formation, SiGe reliability still benefits from a reduced bulk oxide trapping thanks to favorable energy decoupling of channel carriers to dielectric defect levels. Reduced NBTI is observed in narrow fins, thanks to a reduced oxide electric field. Fin rotation does not improve NBTI in SiGe fins, while some improvement, particularly of the near-interface degradation, was obtained by HPA. Our results show that Si-cap-free RMG SiGe gate stacks with properly optimized HPA can offer a simplified FinFET integration, with a limited reliability penalty compared to best-in-class Si-passivated SiGe devices.

We utilize a very sensitive electron paramagnetic resonance technique called spin-dependent recombination to observe and identify defect centers generated by modest negative bias and moderately elevated temperatures in fully processed p-channel metal-oxide-silicon field-effect transistors. The defects include two Si∕SiO2 interface silicon dangling bond centers (Pb0 and Pb1) and may also include an oxide silicon dangling bond center (E′). Our observations strongly suggest that both Pb0 and Pb1 defects play major roles in the negative bias temperature instability.

A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by ID−VD characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator (PDO) method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous on-the-fly method. It is found that both reaction–diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90°C and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction–diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction–diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.

We have studied the recovery behavior observed in negative bias temperature instability (NBTI) from the aspect of bulk hole traps. Using the maximum entropy method to analyze isochronal annealing data, we evaluated the contributions of bulk hole traps with energy level Et to the initial threshold voltage shifts just after NBT stresses, ΔVOTi(Et). Their shapes are Gaussian-like depending on the NBT stress temperatures, and ΔVOTi(Et) can explain NBTI recovery behaviors as well as the universality. The validity of a previously proposed empirical function describing NBTI recovery curves was confirmed, and the physical meanings of that function were examined. This study proves the importance of hole detrapping events and sheds light on the NBTI recovery mechanism.

Negative Bias Temperature Instability (NBTI) is a critical reliability issue and becoming more and more seriously in the modern CMOS technology. Many models have been proposed to account for the NBTI phenomena, but most of the models are based on the popular hydrogen reaction-diffusion (R-D) mechanisms. For the first time, in this work, a neutral interface-trap model due to the random variations of bond angles and lengths of Si··Si, Si··O and Si··N bonds is applied to explain the NBTI phenomena. The unified compact model with the neutral interface traps can very well characterize stressed device performance. The neutral interface traps with energy distribution in the silicon energy gap can very well account for the root cause of NBTI fast recovery. The model is verified by TCAD simulation and experimental measurement with excellent agreement

In this paper, we have modeled the results of negative bias temperature instability (NBTI) degradation obtained by using charge pumping and linear drain current techniques in the same time measurement setup. The proposed model is based on Hydrogen molecule (H2) cracking at trapped hole center (E' center) to explain the decrease of oxide trapped charge at long NBTI stress time (t > 1000s). In fact, according to experimental data, which are obtained in the framework of the above cited setup, NBTI induces oxide trap generation at earlier stress time followed later by a decrease (annealing) at long stress time. This behavior looks like annealing in radiation effect on gate oxide in MOSFET, which is explained by H2 cracking model. Based on this similarity, we extended this model to NBTI effect. The extended model presents a perfect correlation with the experimental data.