Auto‐tuning PID controller design using a sliding‐mode approach for DC servomotors

The goal of this paper is to implement the secretion mechanism of the Thyroid Hormone (TH) based on bio-mathematical differential eqs. (DE) on an FPGA chip. Hardware Descriptive Language (HDL) is used to develop a behavioral model of the mechanism derived from the DE. The Thyroid Hormone secretion mechanism is simulated with the interaction of the related stimulating and inhibiting hormones. Synthesis of the simulation is done with the aid of CAD tools and downloaded on a Field Programmable Gate Arrays (FPGAs) Chip. The chip output shows identical behavior to that of the designed algorithm through simulation. It is concluded that the chip mimics the Thyroid Hormone secretion mechanism. The chip, operating in real-time, is computer-independent stand-alone system.

In this paper, we introduce a new development system for creating real-time image processing hardware using custom computing machines with multiple Field Programmable Gate Array (FPGA) chips. Three distinct processes are accomplished within the development system: design entry, verification, and translation. A library of modules that implement common low-level machine vision functions is used to create complex designs based on a dataflow graph representation. The library's low-level image processing modules contain both gate-level and chip-level hardware components, of which the gate-level components are compiled into the functionality of available FPGA chips. Standard interfaces are established for input/output of the modules, allowing for the creation of sophisticated software support tools. Experimental results verify the utility of this development system for easily creating real-time machine vision hardware using multiple FPGA-based custom computing machines.

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip.

Raman spectrometer has been widely used as an identification tool for analyzing material structure and composition in many fields. However, Raman scattering echo signal is very weak, about dozens of photons at most in one laser plus signal. Therefore, it is a great challenge to design a Raman spectrum data acquisition system which could accurately receive the weak echo signal. The system designed in this paper receives optical signals with the principle of photon counter and could detect single photon. The whole system consists of a photoelectric conversion module H7421-40 and a photo counting card including a field programmable gate array (FPGA) chip and a PCI9054 chip. The module H7421-40 including a PMT, an amplifier and a discriminator has high sensitivity on wavelength from 300nm to 720nm. The Center Wavelength is 580nm which is close to the excitation wavelength (532nm), QE 40% at peak wavelength, Count Sensitivity is 7.8*10⁵(S^-1PW^-1) and Count Linearity is 1.5MHZ. In FPGA chip, the functions are divided into three parts: parameter setting module, controlling module, data collection and storage module. All the commands, parameters and data are transmitted between FPGA and computer by PCI9054 chip through the PCI interface. The result of experiment shows that the Raman spectrum data acquisition system is reasonable and efficient. There are three primary advantages of the data acquisition system: the first one is the high sensitivity with single photon detection capability; the second one is the high integrated level which means all the operation could be done by the photo counting card; and the last one is the high expansion ability because of the smart reconfigurability of FPGA chip.

Regular Expressions (RegExes) are widely used in various applications to identify strings of text. Their flexibility, however, increases the complexity of the detection system and often limits the detection speed as well as the total number of RegExes that can be detected using limited resources. The two classical detection methods, Deterministic Finite Automaton (DFA) and Non-Deterministic Finite Automaton (NFA), have the potential problems of prohibitively large memory requirements and a large number of concurrent operations, respectively. Although recent schemes addressing these problems to improve DFA and NFA are promising, they are inherently limited by their scalability, since they follow the state transition model in DFA and NFA, where the state transitions occur per each character of the input. We recently proposed a scalable RegEx detection system called Lookahead Finite Automata (LaFA) to solve these problems with three novel ideas: 1. Provide specialized and optimized detection modules to increase resource utilizations. 2. Systematically reordering the RegEx detection sequence to reduce number of concurrent operations. 3. Sharing states among automata for different RegExes to reduce resource requirements. In this paper, we propose an efficient hardware architecture and prototype design implementation based on LaFA. Our proof-of-concept prototype design is built on a fraction of a single commodity Field Programmable Gate Array (FPGA) chip and can accommodate up to twenty-five thousand (25k) RegExes. Using only 7% of the logic area and 25% of the memory on a Xilinx Virtex-4 FX100, the prototype design can achieve 2-Gbps (gigabits-per-second) detection throughput with only one detection engine. We estimate that 34-Gbps detection throughput can be achieved if the entire resources of a state-of-the-art FPGA chip are used to implement multiple detection engines.

A field-programmable gate array (FPGA)-based intelligent dynamic sliding-mode control (IDSMC) using recurrent wavelet neural network (RWNN) estimator is proposed to control the mover position of a linear ultrasonic motor (LUSM) in this study. First, the structure and operating principles of the LUSM are introduced briefly. Then, the dynamics of LUSM mechanism with the introduction of a lumped uncertainty, which include the friction force, is derived. Since the dynamic characteristics and motor parameters of the LUSM are non-linear and time-varying, an IDSMC using RWNN estimator is designed to achieve robust control performance of the LUSM drive system. The RWNN estimator is employed to estimate the non-linear functions including the system parameters and external disturbance. Moreover, the adaptive learning algorithm trained the parameters of the RWNN online is derived using the Lyapunov stability theorem. Furthermore, an FPGA chip is adopted to implement the developed control and on-line learning algorithms for possible low-cost and high-performance industrial applications. The experimental results show that excellent positioning and tracking performance are achieved. In addition, the robustness to parameter variations and friction force can be obtained as well using the proposed control system.

In order to reduce the resources utilization of Field Programmable Gate Array (FPGA) chip thereby using one FPGA to control multiple motors together, a novel time-division multiplexing (TDM) method is proposed in this paper. The field-oriented control (FOC) algorithm is developed using Xilinx system generator (XSG) in Matlab/Simulink environment. Due to the fast calculation speed of FPGA and the pipeline optimization technology, the execution time of FOC algorithm can reach 100 kHz. In order to verify the proposed TDM method, the dual-motor scenario is studied in this paper. Experimental results show that by adopting the proposed TDM method, the resource utilization of the FPGA chip can be further greatly reduced.

The mitigation of single event upset (SEU) in SRAM based Field Programmable Gate Array (FPGA) is increasingly important as it is widely used in radiation environments such as space. As D flip-flop (DFF) and memory (including Block RAM and Configuration RAM) are the key elements in FPGAs, it is crucial to develop radiation hardening techniques for enhanced reliability of the DFF and memory. A novel hardened memory design for FPGA is proposed with multi-bit upset (MBU) protection. We further developed two prototype FPGA chips, one with and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13μm CMOS process and have a volume of 3 million equivalent logic gates. In contrast to the base FPGA, the SEU cross section of the memory in the hardened FPGA is at least three orders of magnitude lower. Also, no SEU upsets are observed in the DFF of the hardened FPGA.

The soft computing algorithms are being nowadays used for various multi input multi output complicated non linear control applications. This paper presented the development and implementation of back propagation of multilayer perceptron architecture developed in FPGA using VHDL. The usage of the FPGA (Field Programmable Gate Array) for neural network implementation provides flexibility in programmable systems. For the neural network based instrument prototype in real time application. The conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGA have higher speed and smaller size for real time application than the VLSI design. The challenges are finding an architecture that minimizes the hardware cost, maximizing the performance, accuracy. The goal of this work is to realize the hardware implementation of neural network using FPGA. Digital system architecture is presented using Very High Speed Integrated Circuits Hardware Description Language (VHDL)and is implemented in FPGA chip. MATLAB ANN programming and tools are used for training the ANN. The trained weights are stored in different RAM, and is implemented in FPGA. The design was tested on a FPGA demo board. Keywords- Backpropagation, field programmable gate array (FPGA) hardware implementation, multilayer perceptron, pressure sensor, Xilinx FPGA.

Xilinx and Mathworks jointly proposed System Generator (SysGen) and Simulink to accelerate development of DSP (digital signal processing) style applications on Field Programmable Gate Array (FPGA) chips. However, most of developments with Simulink and SysGen end at simulation stage without complete stand-alone implementation on FPGA since these tools do not come up with sufficient IO system libraries. In this paper, we present the process of implementing a full system to reconstruct CT (computed tomography) images on FPGA using Simulink and SysGen. In this process, we solve technical issues regarding algorithm mapping, design of additional modules, system IO library and resource allocation. Our experience will be taken as useful reference for researchers working on FPGA applications and high resolution medical image applications.

In this paper, a new control method for a interleaved voltage-doubler boost converter is proposed to extend the operating range of duty ratio. Firstly, the analysis of the current-sharing mechanism is presented. Then, the averaging method is adopted to construct an average-behavior circuit model. After that, the modulation signal for current-sharing is particularly designed by amp-second balance. Besides, the average state-space equation of the voltage-doubler can be obtained. The open-loop transfer function can be derived from the small-signal analysis, and the proportional-integral (PI-type) controller parameters can be selected by Bode plots. All the algorithms are implemented in a Field Programmable Gate Array (FPGA) chip. The simulation and experimental results validate the inductor current-sharing capability of the proposed method.

Deep Packet Inspection (DPI) technology has been widely deployed in Network Intrusion Detection System (NIDS) to detect attacks and viruses. State-of-the-art NIDS uses Deterministic Finite Automata (DFA) to perform regular expression matching for its stable matching speed. However, traditional DFA algorithm’s throughput is limited by the input character’s width (usually one character per time). In this paper, we present an architecture named Parallel-DFA to accelerate regular expression matching by scanning multiple characters per time. Experimental results show that, our architecture can achieve as high as 1200 Gbps (1.17 Tbps) rate on current single Field-Programmable Gate Array (FPGA) chip. This makes it a very practical solution for NIDS in 100G Ethernet standard network, which is currently the fastest approved standard of Ethernet. To the best of our knowledge, this is the fastest matching performance architecture on a single FPGA chip. Besides, the throughput is nearly 3 orders of magnitude (916\(\times \)) than that of original DFA implemented on software. Our architecture is about 183.2\(\times \) efficiency than that of original DFA.

A hybrid supervisory control system using a recurrent fuzzy neural network (RFNN) is proposed to control the mover of a permanent magnet linear synchronous motor (PMLSM) servo drive for the tracking of periodic reference inputs. First, the field-oriented mechanism is applied to formulate the dynamic equation of the PMLSM. Then, a hybrid supervisory control system, which combines a supervisory control system and an intelligent control system, is proposed to control the mover of the PMLSM for periodic motion. The supervisory control law is designed based on the uncertainty bounds of the controlled system to stabilize the system states around a predefined bound region. Since the supervisory control law will induce excessive and chattering control effort, the intelligent control system is introduced to smooth and reduce the control effort when the system states are inside the predefined bound region. In the intelligent control system, the RFNN control is the main tracking controller which is used to mimic a idea control law and a compensated control is proposed to compensate the difference between the idea control law and the RFNN control. The RFNN has the merits of fuzzy inference, dynamic mapping and fast convergence speed, In addition, an online parameter training methodology, which is derived using the Lyapunov stability theorem and the gradient descent method, is proposed to increase the learning capability of the RFNN. The proposed hybrid supervisory control system using RFNN can track various periodic reference inputs effectively with robust control performance.

Modern Field Programmable Gate Arrays (FPGAs) posses small features, and have gained popularity in mission-critical systems. However, due to small FPGA features and harsh external conditions that can be faced by a mission-critical system, an FPGA chip can suffer from faults. This in turn raises the need to test an FPGA to ensure a reliable system performance. However, a mission-critical system requires that the test process should be non-intrusive, i.e., applications & FPGA regions that are not being tested remain unaffected. Hence, an online test scheme is required that not only verifies the correctness of an FPGA, but also does not degrade the performance of other, running FPGA applications. In this paper, we propose a Hardwired Network on Chip (HWNoC) as the Test Access Mechanism (TAM). Our online test scheme uses a HWNoC, to perform real-time streaming of test data that is non-intrusive to other communication traffic. Additionally, our online test scheme exhibits approx. 18 and 29 times lower spatial and temporal overheads as compared to existing schemes, respectively.

Face detection has been widely used in many fields such as security, intelligent human interface etc., and concerns on how to meet the criterion of miniature and real-time have gradually become independent research topics. Traditionally, systems of face detection/recognition are either implemented in very specific hardware or software system. This paper tailors an algorithm of face detection using skin color and presents an efficient implementation on a single Field Programmable Gate Array (FPGA) chip. The implementation exploits the inherit parallelism of hardware and takes advantages of hardware multiply-accumulate units and shift register(RAM-Based) units on FPGA. The entire system uses a single FPGA coupled to a pair of SDRAM chips, and no extra parts. The system was implemented and tested with face detection on a 1280×1024 frame taking 16.66 ms (60 frames per second ). This system can be used as a reference for lightweight embedded vision systems.