Automated task distribution in multicore network processors using statistical analysis

SummaryMulticore network processors have been playing an increasingly important role in computational processes, which emphasize on scalability and parallelism of the systems, in distributed environments especially in Internet‐based delay‐sensitive applications. It is an important but unsolved issue, however, to efficiently schedule tasks in network processors with multicore and multithread for improving the system throughput as much as possible. Profiling can gather runtime environment information and guide the compiler to optimize programs through scheduling tasks based on the runtime context. This paper proposes a profiling‐based task scheduling approach, targeting on improving the throughput of multicore network processor (Intel IXP) systems in the balanced pipeline way. In this work, we investigate a profiling‐based task scheduling framework, a task scheduling algorithm, and a set of performance models. Our task allocation scheme maps tasks onto the pipeline architecture and multiple threads of network processors in parallel, which incorporates the profiling context and global thread refinement. We evaluate our task scheduling algorithm by implementing representative network applications on the Intel IXP network processor. Experimental results demonstrate that our algorithm is able to schedule tasks in a balanced pipeline fashion and achieve the high throughput and data transmission rate. Copyright © 2012 John Wiley & Sons, Ltd.

With the development of high-speed network, the demand of high performance network processing keeps rising. Multi-core network processors (NPs), specially designed for network processing, are widely used in a variety of network applications to achieve high throughput. However, when using TCP stack of Linux which runs on the multi-core network processor to transmit data across the network, the performance is far from optimal. In this paper, a multi-path reliable data transfer (MPRDT) system based on multi-core network processors is proposed to get higher performance. The proposed system implements a UDP-based reliable data transfer stack in the real-time operating system (RTOS) of the multi-core network processors. Furthermore, a multi-path method is applied to enable the system to manage multi-path connections through different interfaces to different receiver ends, taking full use of the network interfaces and bandwidth resources. The experimental results indicate that the MPRDT can manage multipath connections properly and get higher throughput with less consumption of CPU resource than the Linux scheme.

In this paper, we explore the effect of cross-training workers in Dual Resource Constrained (DRC) systems with machines having different mean processing times. By means of queuing and simulation analysis, we show that the detrimental effects of pooling (cross-training) previously found in single resource constrained (SRC) heterogeneous systems are also apparent in DRC heterogeneous systems. Fully cross-training workers in DRC heterogeneous systems is only beneficial if the differences between mean processing times are not too large, otherwise cross-training should be pursued within homogeneous subgroups of machines. Due to the limited machine availability, DRC systems are unable to use some of the potential assignment flexibility from cross-trained workers (pooled queues) that can be used in SRC systems. However, it appears that this restriction in the DRC system may even improve the system mean flow (waiting) time performance compared to the SRC system for relatively large differences in processing time. Finally, in fully flexible multiple server queuing systems, restricting the assignment flexibility by applying a decentral when-rule (i.e. a commonly used labour assignment rule in practice and research) instead of a central when-rule also seems to improve the mean flow time performance under processing time differences.

A network processing unit (NPU) is increasingly becoming the processor of choice for building custom packet-processing gateways. In this paper, we present an NPU-based design and architecture for a packet data serving node (PDSN) in a CDMA2000 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∗</sup> network. A PDSN is a packet-processing gateway that interfaces between the Internet and the wireless radio access network to provide packet data services to mobile users. We map the different functions of the PDSN onto the packet-processing engines and the core processor of an NPU. This involves a complete separation of the control plane, which is implemented in the core processor, and the data plane, which is implemented using a multistage packet pipeline mapped onto the packet-processing engines. We describe resource allocation schemes for packet buffering and processing and also a flexible communication method with the core processor. The mechanisms described in the paper are general enough to be used to implement other NPU-based packet-processing gateways. We also present a prototype implementation of the PDSN on an NPU and show its superiority to commercial products by means of measurement experiments.

Stroke is a leading cause of disability and impaired arm function is a common consequence. Constraint-induced movement treatment is a technique used to increase weak arm use and to decrease motor deficits resulting from stroke. Eleven stroke survivors participated in a constraint-induced movement treatment protocol of 3 ½ hours of treatment per day for 8 days. Participants experienced significantly increased use of the weak arm in daily activities, which was measured by the Motor Activity Log, and a trend toward improved coordination in the weak arm, which was measured by the Wolf Motor Function Test. Participants did not report significant improvements in average performance or satisfaction in self-identified occupational performance problems. When these problems were analyzed individually, no significant differences were seen immediately post-treatment. However, significant improvements were seen for satisfaction at 4 to 6 months post-treatment. The occupational performance problems identified by the participants were equally divided between problems related to hand use and problems not related to hand use. Approximately half of the non-hand use problems involved endurance. Although participants in this study did make improvements in arm use and coordination, they did not identify improvements in average occupational performance or satisfaction as an outcome of constraint-induced movement treatment.

MOR – C photography is a company that offer services for digital camera and lens be based order by customer, the production process used sequence method to avoid lateness in service order. The author is using description method in research method. The research is doing by case study in production process of service company, and then identification various of factor that influence production process. The technique to collected actual data from the service company, the author used interview, observation, and documentary data from company.In sequencing method there are many method used by companies in general like FCFS (First Come, First Serve), SPT (Short Processing Time), LPT (Longest Processing Time), EDD (Earlier Due Date), and CR (Critical Ratio). MOR – C photography used FCFS method in sequence of service order, but still occured lateness in order first week 12,8 days; second week 11,8 days; third week 17,9 days; and fourth week 13,1 days. MOR – C photography should use SPT method to finished the order be based short processing time and routine controling total of order. SPT method will be more effective with batch system, is system that collected amount of order be based short processing time and then processing them. Keywords : Sequence Method; FCFS (First Come, First Serve); SPT (Short Processing Time); LPT (Longest Processing Time); EDD (Earlier Due Date); CR (Critical Ratio)

In this paper a new intelligent control architecture for autonomous multi-robot systems is presented. Furthermore, the paper deals with task description, task distribution, task allocation and coordination of the system components. The main advantage of the new control architecture is the distributed execution of tasks or subtasks by components of the multi-robot system. The components are able to build teams dynamically thereby avoiding the bottle neck problem of the information flow in centralized controlled architectures. The communication and cooperation between components to achieve distributed organized control architectures is studied. The described intelligent control architecture is to replace the former control architecture of the autonomous robot KAMRO. >

One of the most frequent issues in multiple robot implementation is task allocation with the lowest path cost. Our study addresses the multi‐robot task allocation challenge with path costs, the lowest computing time, and task distribution. Furthermore, it is usual for a robot's processing capabilities to be restricted to operate in various target environments. As a consequence, adequate processing power consumption would demonstrate the system's efficiency. Task allocation and path planning issues must be addressed regularly to ensure multi‐robot system operation. Task allocation and path planning issues must be addressed regularly to ensure multi‐robot system operation. The above‐mentioned serious challenge gets more complicated when system factors such as robots and tasks multiply. As previously stated, this article solves the issue using a fuzzy‐based optimum path and reverse auction‐based methods. The detailed simulation results indicate that the suggested methods can solve task allocation with the lowest path cost. A comparative study is conducted between the suggested algorithm and two existing commonly used techniques, the auction‐based and the Hungarian algorithms. Finally, the suggested method was run in real‐time on a TurtleBot2 robot. The findings show the suggested algorithm's efficiency and simplicity of implementation.

Prevailing trend in design of chip multiprocessors (CMP) has been that single-core processors are replicated. Therefore, they typically define asynchronous computational model, require heavily locality-aware memory allocation, and present high overheads in intercommunication. This kind of properties make parallel programming very challenging and prone to errors. We introduce our new dual-mode MultiBunched/Threaded Architecture with Chaining (MBTAC) processor core, the main building block of the REPLICA CMP. It provides a modern, sophisticated way for writing general purpose parallel programs backed up by native execution capabilities/realization of key concepts. These include support for cost-efficient machine instruction-level synchronization and uniform shared global memory for enabling easy-to-program memory allocation of data structures and data movement. MBTAC makes use of low-overhead thread-context switching solution; it has parallel computing savvy functional unit organization to exploit inter-thread instruction-level parallelism and highly efficient multioperations. To evaluate the goodness of our proposal, we implemented three MBTAC constellations featuring up to 2048 parallel threads on FPGA, compared it with respect to DLX and Intel’s Core i7 processors. The results point toward high performance in communication-intensive problems, simplified parallel programmability, and regular, implementation-friendly structure.

BackgroundApproximately 30% of individuals with stroke experience impending cognitive decline, often leading to dementia over the subsequent years. Despite an increased risk of dementia among individuals with stroke, there is no predictive tool to identify stroke individuals who are at higher risk of future cognitive decline. The purpose of the Come‐Drive study is to identify whether dual impairments in cognitive and motor function may provide behavioral biomarkers to predict future cognitive decline in stroke.MethodThirty‐two stroke survivors (cognitively impaired; N = 16 and cognitively normal; N = 16) participated. All participants performed (1) Cognitive tasks: A divided attention task provided mean processing time. A simple reaction time task with the unaffected upper extremity provided an index of variability in processing time. (2) Motor tasks: Overground walking to provide gait speed and gait (stride time) variability measurements. Hierarchical logistic regression analyses were performed to determine whether processing speed and/or gait performance predicted participants’ cognitive status.ResultThe cognitively impaired stroke group showed significantly increased mean processing time (p = 0.001), and increased variability in processing time (p = 0.005), compared to the cognitively normal stroke group. The cognitively impaired stroke group showed slower gait speed and amplified gait variability, but these differences failed to reach statistical significance (p &gt; 0.05). The logistic regression showed that the mean and variability of processing time significantly predicted the cognitive status in the individuals with stroke (X2 (4) = 17.29, p = 0.002). Gait speed and gait variability did not emerge as significant predictors of cognitive status in individuals with stroke. The regression model accounted for 58% of the variance in determining the cognitive status post‐stroke with 83% accuracy.ConclusionDual decline in processing speed and gait did not emerge to be better predictors of cognitive status in individuals with stroke than the decline in processing speed alone. Perhaps a more complex motor task may serve as a better predictor of cognitive decline than a simple overground walking task. Overall, unique impairments in cognitive processing speed may serve as indicators of poor cognitive status in individuals with stroke.

In this paper, we show that the problem of configuring the topology of a data center network to optimize data aggregation is NP-hard even when the number of aggregators is 1. Further, the approximation ratio of the algorithm proposed by Wang, Ng, and Shaikh [3] for the case of a single aggregator is (k+1)/2, where k is the degree of ToR (top-of-rack) switches and this algorithm also exhibits an anomalous behavior-increase in the switch degree may result in an increase in the aggregation time. By comparison, if topology configuration is done using the longest processing time (LPT) scheduling rule, the approximation ratio is (4/3-1/(3k)). We show that for every instance of the single aggregator topology configuration problem, the time required to aggregate using the LPT configuration is no more than that using the Wang et al. rule. By coupling the LPT rule with the rule of Wang et al., we achieve a better throughput as promised by LPT and at the same time reduce the total network traffic. Experimental results show that the LPT rule reduces aggregation time by up to 90% compared to the Wang et al. rule. The reduction in aggregation time afforded by a known improvement, COMBINE, of LPT relative to Wang et al. is up to 90.5%. More interestingly, when either of the LPT rule or COMBINE is augmented with the Wang et al. rule, total network traffic is reduced by up to 90% relative to using LPT and COMBINE with chains.

This paper proposes an architecture that permits selected application- and middleware-level functionality to be 'pushed into' network processors. Such functionality is represented as stream handlers that run on the network processors (NPs) attached to the host nodes participating in overlay networks. When using stream handlers, application- and middleware-level functionality is 'split' into multiple components that are jointly executed by the host and the attached NP (ANP). Resulting improvements in application performance are due to the network-near nature of ANPs and due to the ability to dynamically customize stream handlers to meet current application needs or match current network resources. The evaluation of our current prototype implementation indicates that the use of ANP-level handlers can reduce the delays on the application data path by more than 25%, and can sustain higher throughput for the application services provided by stream handlers. In addition, stream handlers are a suitable basis for scalable implementations of data-increasing services like destination-customized multicast.

Higher signal precision helps to predict returns more accurately. But higher signal precision requires higher more costs and longer time. The acquisition of higher precision signals has two opposite effects for investors. First, the higher precision helps with return forecast. Second, the longer processing time is a disadvantage for decision making. We build a rational expected model under the assumption that the longer processing time takes, the higher the signal precision. The results show that higher signal precision is not always better after considering signal processing time. There is an optimal signal waiting time for investors.

Today, designers of network processors strive to keep the packet reception and transmission orders identical, and therefore avoid any possible out-of-order transmission. However, the development of new features in advanced network processors has resulted in increasingly parallel architectures and increasingly heterogeneous packet processing times, leading to large reordering delays. In this paper, we introduce novel scalable scheduling algorithms for preserving flow order in parallel multi-core network processors. We show how these algorithms can reduce reordering delay while adapting to any load-balancing algorithm and keeping a low implementation complexity overhead. To do so, we use the observation that all packets in a given flow have similar processing requirements and can be described with a constant number of logical processing phases. We further define three possible knowledge frameworks of the time when a network processor learns about these logical phases, and deduce appropriate algorithms for each of these frameworks. Finally, we model our proposed algorithms and simulate them under both synthetic traffic and real-life traces, and show that they significantly outperform past approaches.

We developed and evaluated a visual compensation system that allows surgeons to visualize obscured regions in real time, such that the surgical instrument appears virtually transparent. The system consists of two endoscopes: a main endoscope to observe the surgical environment, and a supporting endoscope to render the region hidden from view by surgical instruments. The view captured by the supporting endoscope is transformed to simulate the view from the main endoscope, segmented to the shape of the hidden regions, and superimposed to the main endoscope image so that the surgical instruments look transparent. A prototype device was benchmarked for processing time and superimposition rendering error. Then, it was evaluated in a training environment with 22 participants performing a backhand needle driving task with needle exit point error as the criterion. Lastly, we conducted an in vivo study. In the benchmark, the mean processing time was 62.4ms, which was lower than the processing time accepted in remote surgeries. The mean superimposition error of the superimposed image was 1.4mm. In the training environment, needle exit point error with the system decreased significantly for experts compared with the condition without the system. This change was not significant for novices. In the in vivo study, our prototype enabled visualization of needle exit points during anastomosis. The benchmark suggests that the implemented system had an acceptable performance, and evaluation in the training environment demonstrated improved surgical task outcomes in expert surgeons. We will conduct a more comprehensive in vivo study in the future.