Automated transformation of algorithms into register-transfer level implementations

The rapidly increasing complexities of hardware designs are forcing design methodologies and tools to move to the Electronic System Level (ESL), a higher abstraction level with better productivity than the state-of-the-art Register Transfer Level (RTL). Behavioral synthesis, which automatically synthesizes ESL behavioral specifications to RTL implementations, plays a central role in this transition. However, since behavioral synthesis is a complex and error-prone translation process, the lack of designers' confidence in its correctness becomes a major barrier to its wide adoption. Therefore, techniques for establishing equivalence between an ESL specification and its synthesized RTL implementation are critical to bring behavioral synthesis into practice. The major research challenge to equivalence checking for behavioral synthesis is the significant semantic gap between ESL and RTL. The semantics of ESL involve untimed, sequential execution; however, the semantics of RTL involve timed, concurrent execution. We propose a sequential equivalence checking (SEC) framework for certifying a behavioral synthesis flow, which exploits information on successive intermediate design representations produced by the synthesis flow to bridge the semantic gap. In particular, the intermediate design representation after scheduling and pipelining transformations permits effective correspondence of internal operations between this design representation and the synthesized RTL implementation, enabling scalable, compositional equivalence checking. Certifications of loop and function pipelining transformations are possible by a combination of theorem proving and SEC through exploiting pipeline generation information from the synthesis flow (e.g., the iteration interval of a generated pipeline). The complexity brought by bubbles in function pipelines is creatively reduced by symbolically encoding all possible bubble insertions in one pipelined design representation. The result of this dissertation is a robust, practical, and scalable framework for certifying RTL designs synthesized from ESL specifications. We have validated the robustness, practicality, and scalability of our approach on industrial-scale ESL designs that result in tens of thousands of lines of RTL implementations.

Describes an approach to the synthesis of VLSI systems from their high-level behavioral descriptions into structural implementations. This approach integrates operation scheduling, data-path allocation, and control allocation of a traditional synthesis process. Therefore, the advantages from compacting the data path, for example, can be compared immediately with the possible expansion of the control logic to justify the compaction. The horizontal algorithm is designed to make decisions on what should be done in each synthesis step. When making such design decisions, it makes tradeoffs between the data path and control, resource sharing, and operation scheduling, as well as cost and performance. The experimental results show that under the same conditions, a horizontal approach performs better than a vertical approach with respect to overall system performance and estimated layout area. The proposed horizontal optimization algorithm was designed and implemented in computer-aided design and manufacturing. >

Today's Systems-on-Chips (SoCs) comprise general/special purpose programmable processors and specialized hardware modules referred to as accelerators. These accelerators serve as co-processors and are invoked through software or firmware. Thus, verifying SoCs requires co-verification of hardware with software/firmware. Co-verification using cycle-accurate hardware models is often not scalable, and requires hardware abstractions. Among various abstractions, architecture-level abstractions are very effective as they retain only the software visible state. An Instruction-Set Architecture (ISA) serves this role for processors and such ISA-like abstractions are also desirable for accelerators. Manually creating such abstractions for accelerators is tedious and error-prone, and there is a growing need for automation in deriving them from existing Register-Transfer Level (RTL) implementations. An important part of this automation is determining which state variables to retain in the abstract model. For processors and accelerators, this set of variables is naturally the Architectural State Variables (ASVs) - variables that are persistent across instructions. This paper presents the first work to automatically determine ASVs of processors and accelerators from their RTL implementations. We propose three novel algorithms based on different characteristics of ASVs. Each algorithm provides a sound abstraction, i.e., an over-approximate set of ASVs. The quality of the abstraction is measured by the size of the set of ASVs computed. Experiments on several processors and accelerators demonstrate that these algorithms perform best in different cases, and by combining them a high quality set of ASVs can be found in reasonable time.

Background: In recent years, the rising demand for high-performance radar systems in aeronautics, astronautics, national defense, and civil communication has driven the widespread application of phased-array technology. The design of beam controllers, the core of phased-array systems, faces many challenges. Traditional implementation schemes are usually based on application-specific integrated circuits (ASIC) or discrete components, which have a long development cycle, poor flexibility, and limited adaptability. Field-programmable gate arrays (FPGA), with their high parallelism, reconfigurability, and powerful signal processing capabilities, offer a new way to implement phased-array control systems. But FPGA design has traditionally relied on register transfer level (RTL) description, which is inefficient and struggles to keep up with the rapid iteration of complex algorithms. With the development of high-level synthesis (HLS) technology, it has become possible to develop FPGAs using high-level languages such as C/C++. However, improving development efficiency while ensuring hardware performance remains a key issue in the design of phased-array beam controllers. Materials and Methods: This study employs an HLS - RTL co - design method to build a phased - array beam controller. This approach combines the strengths of HLS's efficient algorithm implementation and RTL's precise hardware interface control. The system architecture consists of three parts: the host - machine control layer, FPGA processing layer, and phase - control output layer. In the FPGA processing layer, the core beam - forming algorithm is implemented via HLS. Based on phased - array principles, this algorithm converts target angles to wave vectors and calculates phase - compensation values for each element in an 8×8 array. Pipelining and parallel processing techniques are used in the HLS design to optimize algorithm throughput and latency. The phase - control output layer, designed with RTL, repackages 64 calculated phase values and distributes them to 16 physical phase - shifter chips. Each phase - shifter manages four elements and receives control data through an SPI interface. Results: The proposed FPGA-based phased-array beam controller design in this paper has successfully achieved high - speed, high - precision beam control. By using the HLS - RTL co - design method, it has solved the problem of low algorithm implementation efficiency in traditional FPGA development and ensured the high performance and reliability of hardware interfaces. Experimental results indicate that the system meets or surpasses design targets on key performance indicators. Its end - to - end latency is kept within 130μs, it supports an angle update rate of over 5,000 times per second, and can satisfy the requirements for tracking highly dynamic targets in practical applications. Conclusion: The major contributions of this research are as follows: presenting an HLS - RTL co - design methodology for complex FPGA system development; designing an efficient phased - array beam - forming algorithm and its hardware implementation; and developing a flexible and scalable phased - array control system architecture that supports different array configurations. These findings are highly significant for beamforming technologies in phased - array radar and 5G communication systems, as well as for other FPGA applications requiring high - speed signal processing.

Sequential equivalence checking between system level descriptions of designs and their register transfer level (RTL) implementations is a very challenging and important problem in the context of systems on a chip (SoCs). We propose a technique to alleviate the complexity of the equivalence checking problem, by efficiently decomposing it using compare points. Traditionally, equivalence checking techniques use nominal or functional mapping of latches as compare points. Since we operate at a level where design descriptions are in system level languages or hardware description languages, we leverage the information available to us at this level in deducing sequential compare points. Sequential compare points encapsulate the sequential behavior of designs and are obtained by statically analyzing the design descriptions. We decompose the design using sequential compare points and represent the design behavior at these compare points by symbolic expressions. We use a SAT solver to check the equivalence of the symbolic expressions. In order to demonstrate our technique, we present results on a non-trivial case study. We show an equivalence check between a SystemC description and two different Verilog RTL implementations of a Viterbi decoder, that is a component of the DRM SoC.

This paper presents the VPN tool (VHDL to Petri Nets) for translating a subset of VHDL'87 into a formal model based on Interpreted and Timed Petri Nets (ITPN). This formal model finds its application to different kind of analysis such as symbolic model checking, behavioral equivalence and behavioral synthesis of the VHDL descriptions.

A critical issue in patient planning is to determine whether the medical processes of a patient can be completed by a time constraint based on the available resources in hospitals. The problem is a Temporal Constraint Satisfaction Problem (TCSP). The objectives of this paper are to propose a viable and systematic approach to develop a distributed cooperative problem solver for TCSP and estimate the shortest and the longest completion time for handling a patient in the presence of uncertainty based on Multi-agent systems (MAS) architecture. Our approach combines MAS with a subclass of time Petri net (TPN) models to solve TCSP. Existing analysis methods of TPN based on state classes cannot be applied directly due to distributed architecture of MAS. In this paper, a temporal analysis method based on MAS architecture is proposed. Our temporal analysis method efficiently deduces the earliest and latest completion time of a patient based on interaction between agents.

This paper presents a non-scan design-for-testability (DFT) method for VLSIs designed at register transfer level (RTL) to achieve complete fault efficiency. In RTL design, a VLSI generally consists of a controller and a data path. The controller and the data path are connected with internal signals: control signals and status signals. The proposed method consists of the following two steps. First, we apply our DFT methods to the controller and the data path, respectively. Then, to support at-speed testing, we append a test plan generator which generates a sequence of test control vectors for the modified data path. Our experimental results show that the proposed method can reduce significantly both of test generation time and test application time compared with the full-scan design, though the hardware overhead of our method is slightly larger than that of the full-scan design.

A PN-based approach to the high-level synthesis of digital systems

High-level synthesis operates on internal models known as control/data flow graphs (CDFG) and produces a register-transfer-level (RTL) model of the hardware implementation for a given schedule. For high-level synthesis to be efficient it has to estimate the effect that a given algorithmic decision (e.g., scheduling, allocation) will have on the final hardware implementation (after logic synthesis). Currently, this effect cannot be measured accurately because the CDFGs are very distinct from the RTL/gate-level models used by logic synthesis, precluding interaction between high-level and logic synthesis. This paper presents a solution to this problem consisting of a novel internal model for synthesis which spans the domains of high-level and logic synthesis. This model is an RTL/gate-level network capable of representing all possible schedules that a given behavior may assume. This representation allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.

In high level synthesis, resource sharing may result in a circuit containing false loops that pose great difficulty in timing validation during design sign-off phase. It is hence desirable to avoid generating any false loops in a synthesized circuit. Previous work considered mainly data path sharing for false loop elimination. However, for a complete circuit with both data path and control path, false loops can be created due to control logic sharing, even though the loops caused by data path sharing have all been removed. In this paper we present a novel approach to detect and eliminate the false loops caused by control logic sharing. An effective filter is devised to reduce the computation complexity of false loop detection, which is based on checking the level numbers that are propagated from data path operators to inputs/outputs of the control path. Only the input/output pairs of the control path identified by the filter are further investigated by traversing into the data path for false loop detection. A removal algorithm is then applied to eliminate the detected false loops, followed by logic minimization to further optimize the circuit. Experimental results show that for nine example circuits we tested, the final designs after false loop removal and logic minimization give only slightly larger area than the original ones that contain false loops.

In recent years, integrating high-level synthesis and physical design has become essential for successful timing closure. In this paper, we present a novel probabilistic approach to perform integrated datapath allocation and floorplanning. In contrast to existing methodologies that tradeoff high-level design space searched with accuracy of physical estimates, the proposed methodology performs exhaustive high-level synthesis (datapath allocation) with heuristic floorplanning. Exhaustive search guarantees optimal allocation results. Heuristic floorplanning imparts flexibility to update the floorplan while constructing the allocation solution. This improves accuracy of the floorplan estimates used. To tackle the increased design space, we propose novel probabilistic-gain measures that predict the impact of an allocation decision on the constraints, prior to the allocation decision being made. The probabilistic-gain measures are used to select allocation decisions that will most likely lead to optimal solutions early, thereby minimizing time-consuming floorplan evaluations of decisions that will most likely lead to sub-optimal solutions. Experimental results confirm the effectiveness of the proposed approach.

The growing complexity of modern digital design makes designers shift toward starting design exploration using high-level languages, and generating register transfer level (RTL) design from system level modeling (SLM) using high-level synthesis or manual transformation. Unfortunately, this translation process is very complex and may introduce bugs into the generated design. In this paper, we propose a novel SLM and RTL sequential equivalence checking method. The proposed method bases on Finite state machines with datapath (FSMD) equivalence checking method. The proposed method recognizes the corresponding path-pairs of FSMDs using machine learning (ML) technique from all the paths. And then it compares the corresponding path-pairs by symbolic simulation. The advantage of our method is that it separates the corresponding path-pairs from all the paths and avoids blind comparisons of path-pairs. Our method can deal with greatly different SLM and RTL designs and dramatically reduce the complexity of the path-based FSMD equivalence checking problem. The promising experimental results show the efficiency and effectiveness of the proposed method.

RTL implementations and FPGA benchmarking of selected CAESAR Round Two authenticated ciphers

High-Level Synthesis (HLS)-based VLSI design flows allow designers to start from high-level specifications in a general-purpose programming language like C/C++ and automatically generate an optimized hardware design in a hardware description language (HDL) like Verilog or VHDL. Supply of compromised computer-aided design (CAD) tools by an electronic design automation (EDA) vendor to the chip designers is a great threat that adversely affects the horizontal semiconductor business model. Recent works have examined the potential for security issues induced by a compromised HLS CAD tool and demonstrated how HLS is a prime candidate for hardware Trojan (HT) insertion into any underlying design since it is hard to correlate the high-level description to the generated register-transfer level (RTL) code. Further, it has been shown that the use of compiler-generated intermediate representation (IR) as a likely attack vector for inserting HT in the RTL during an HLS-based IC design flow, taking advantage of the lack of automated methods to analyse logic inside a complex LLVM IR. In this work, we propose, implement, and evaluate a novel HLS security verification framework by leveraging the modern large language models (LLMs). Specifically, we focus on detecting the HTs introduced using Black-Hat HLS and HLS-IRT toolchain by performing functional verification using LLM. The experimental results show that LLMs have an impressive ability to analyse and automatically identify these hardware security anomalies.