Automatic Industry PCB Board DIP Process Defect Detection with Deep Ensemble Method

A deep ensemble convolutional neural network (CNN) model to inspect printed circuit board (PCB) board dual in-line package (DIP) soldering defects with Hybrid-YOLOv2 (YOLOv2 as a foreground detector and ResNet-101 as a classifier) and Faster RCNN with ResNet-101 and Feature Pyramid Network (FPN) (FRRF) achieved a detection rate of 97.45% and a false alarm rate (FAR) of 20%–30% in the previous study [34] . However, applying the method to other production lines, environmental variations, such as lighting, orientations of the sample feeds, and mechanical deviations, led to the degradation in detection performance. This article proposes an effective self-adaption method that collects “exception data” like the samples with which the Artificial Intelligent (AI) model made mistakes from the automated optical inspection inference edge to the training server, retraining with exceptions on the server and deploying back to the edge. The proposed defect detection system has been verified with real tests that achieved a detection rate of 99.99% with an FAR 20%–30% and less than 15 s of inspection time on a resolution $7296 \times 6000$ PCB image. The proposed system has proven capable of shortening inspection and repair time for online operators, where a 33% efficiency boost from the three production lines of the collaborated factory has been reported [6] . The contribution of the proposed retraining mechanism is threefold: 1) because the retraining process directly learns from the exceptions, the model can quickly adapt to the characteristic of each production line, leading to a fast and reliable mass deployment; 2) the proposed retraining mechanism is a necessary self-service for conventional users as it incrementally improves the detection performance without professional guidance or fine-tuning; and 3) the semiautomatic exception data collection method helps to reduce the time-consuming manual labeling during the retraining process.

Printed circuit boards (PCBs) are primarily used to connect electronic components to each other. It is one of the most important stages in the manufacturing of electronic products. A small defect in the PCB can make the final product inoperable. Therefore, careful and meticulous defect detection steps are necessary and indispensable in the PCB manufacturing process. The detection methods can generally be divided into manual inspection and automatic optical inspection (AOI). The main disadvantage of manual detection is that the detection speed is too slow, resulting in a waste of human resources and costs. Thus, in order to speed up the production speed, AOI techniques have been adopted by many PCB manufacturers. Most current AOI mechanisms use traditional optical algorithms. These algorithms can easily lead to misjudgments due to different light and shadow changes caused by slight differences in PCB placement or solder amount so that qualified PCBs are judged as defective products, which is also the main reason for the high misjudgment rate of AOI detection. In order to effectively solve the problem of AOI misjudgment, manual re-judgment is currently the reinspection method adopted by most PCB manufacturers for defective products judged by AOI. Undoubtedly, the need for inspectors is another kind of labor cost. To reduce the labor cost. of manual re-judgement, an accurate and efficient PCB defect reinspection mechanism based on deep learning algorithm is proposed. This mechanism mainly establishes two detection models, which can classify the defects of the product. When both models have basic recognition capabilities, the two models are then combined into a main model to improve the accuracy of defect detection. In the study, the data provided by Lite-On Technology Co., Ltd. were implemented. To achieve the practical application value in the industry, this research not only considers the problem of detection accuracy, but also considers the problem of detection execution speed. Therefore, fewer parameters are used in the construction of the model. The research results show that the accuracy rate of defect detection is about 95%, and the recall rate is 94%. Compared with other detection modules, the execution speed is greatly improved. The detection time of each image is only 0.027 s, which fully meets the purpose of industrial practical application.

Printed circuit boards (PCBs) are ubiquitous and essential electronic components. Tiny targets and high precision are the focus of PCB defect detection. This paper proposes an improved model focusing on tiny defect detection and model compression to achieve better performance in PCB defect detection. The improved model has a compact structure based on MobileNet v3 Small-CA and an image-cutting layer. Moreover, it applies an improved multi-scale fusion step with a location weighted mechanism to enhance representation performance. The proposed model outperforms state-of-the-art detection algorithms such as Faster R-CNN, EfficientDet, SSD, and YOLO v7, based on experimental results on a public synthetic PCB dataset. The proposed tiny object detection model has better performances on speed and detection accuracy, thereby benefitting the manufacturing industries associated with PCBs.

A radio frequency (RF) front-end module at 5 GHz has been designed and implemented in a conventional printed circuit board (PCB). The module consists of two switches, two bandpass filters, a balun, a low noise amplifier and a power amplifier. Distributed components and sub-circuits based upon the transmission line theory have been utilized for the module design. All the sub-circuits and the entire module have been evaluated by both simulation and measurements. It is shown that RF modules at 5 GHz can be integrated in a PCB utilizing a conventional PCB process. This module integration technique provides not only low cost but also high performance because of the elimination of parasitics associated with lumped components in a conventional design

The conversion to lead-free Ball Grid Array (BGA) packages has raised several new assembly and reliability issues. One reliability concern becoming more prevalent is the increased propensity of pad cratering in Printed Circuit Boards (PCBs) [1, 2]. In general, lead-free solder joints are stiffer than tin-lead solder joints, and some lead-free compatible PCB dielectric materials are more brittle than conventional tin-lead compatible PCB materials. These two factors, coupled with the higher peak reflow temperatures for lead-free assembly, could transfer more strain to the PCB dielectric structure, causing a cohesive failure underneath the BGA corner pads. The likelihood of pad cratering occurring in any given assembly depends on several factors including, but not limited to the BGA package size, construction and surface finish; and the PCB pad size, material and surface finish. Standard assembly level bend and shock tests can be used to determine if the entire assembly can survive a given strain and strain-rate range without having any failures. However, with these standard assembly level tests, it is difficult to determine if the failures occur due to a weaker PCB structure or a stiffer BGA package. It is critical to have a standardized test method that can be used to characterize and rank-order different PCB dielectric materials and PCB pad sizes. In this study, an easy-to-implement test method is presented in detail, along with calibration and test results comparing a broad spectrum of PCB attributes. Different dielectric materials and pad sizes were evaluated to develop a comparative metric that can be used to rank-order different material/pad size combinations. The results were generated over different pull temperatures and multiple reflows, to study the effect of temperature on dielectric mechanical strength characteristics. Ultimately, these metrics can be used to optimize PCB design, thus mitigating pad cratering potential.

Designing pin-fields and related structures will be challenging for emerging 40 Gb/s electrically-based SerDes links. It is not known whether pin-fields implemented in conventional printed circuit board (PCB) technology will be capable of supporting these high data rates. We demonstrate through modeling and measurements that PCB pin-fields appear viable for data rates up to 40 Gb/s, provided that care is taken in the design.

Electronic equipment is exposed to rough vibrations throughout its life cycle. Electronic components can be damaged by these vibrations and could lead to device failure. The conventional Printed Circuit Boards (PCBs) that form the foundation of numerous electronic devices are predominantly constructed from copper films that are bound to fiber epoxy laminates, such as FR4, which is composed of glass fibers, and FR1, which is composed of paper. Being biodegradable makes cellulose a more sustainable choice. Nonetheless, it is imperative to uphold performance criteria, and this work aims to contribute to this assessment. Using simulation studies, we compare the behavior of these two PCBs under vibrational stress. The finite element analysis (FEA) of the vibrations for the PCB samples was modelled using the Ansys software. The FEA simulations show that both types of PCBs have similar movements and accelerations at certain places on the board.

This paper presents inspection of Printed Circuit Boards (PCBs) based on normalized crosscorrelation. Correlation gives the similarity measure of images. In this paper, Normalized Cross-Correlation has been used to differentiate between a defective and defect free printed circuit board. Different PCBs have been inspected using normalized cross-correlation in this paper and further defected PCBs have been used for detection of all possible defects. Image subtraction(one of referential methods) is used for detection of defects of PCBs. And after detection of defects using image subtraction method, the wrong hole defects, missing conductors defects, etching defects, break lines have been classified.

The use of Printed Circuit Board (PCB) technology for device packaging offers new opportunities to solve these challenges. During the past decade embedding of semiconductor chips into PCB structures evolved from a research topic to volume production. The paper will briefly describe this development and categorize today's embedding technologies. First modules with embedded chips are in production in Asia and Europe, mainly for mobile applications. In Europe embedding has gained a strong interest for power modules, especially in automotive applications. Main drivers are the capability for compact and thin packaging, the high reliability and cost saving potential. The automotive industry has a strong demand for highly reliable and cost-efficient electronics. Especially the upcoming generations of hybrid cars and fully electrical vehicles need compact and efficient 400 V power modules. Within the engine compartment installation space is of major concern. Therefore small size and high integration level of the modules are needed. Embedding of power switches, and controller into compact modules using PCB (Printed Circuit Board) technologies offers the potential to reduce the thickness and size of the module. In order to replace DCB ceramics, a structure of thermal laminate material between Cu layers has been developed and the capability for thermal conduction and electrical insulation has been evaluated. For the assembly of large power IGBTs with sizes of 100 mm² and larger, new silver sintering pastes have been evaluated. They enable a pressure-less sintering at 200 °C, compatible with PCB materials. To handle the high switching current of up to 200 A, suitable copper tracks in the PCB are required. The realization of such thick copper lines with thickness up to 1 mm requires advanced processing, compared to conventional multilayer PCB production. In order to form complex power systems out of modules with embedded chips interconnections by Ag sintering are under development.

Defect inspection is essential in the semiconductor industry to fabricate printed circuit boards (PCBs) with minimum defect rates. However, conventional inspection systems are labor-intensive and time-consuming. In this study, a semi-supervised learning (SSL)-based model called PCB_SS was developed. It was trained using labeled and unlabeled images under two different augmentations. Training and test PCB images were acquired using automatic final vision inspection systems. The PCB_SS model outperformed a completely supervised model trained using only labeled images (PCB_FS). The performance of the PCB_SS model was more robust than that of the PCB_FS model when the number of labeled data is limited or comprises incorrectly labeled data. In an error-resilience test, the proposed PCB_SS model maintained stable accuracy (error increment of less than 0.5%, compared with 4% for PCB_FS) for noisy training data (with as much as 9.0% of the data labeled incorrectly). The proposed model also showed superior performance when comparing machine-learning and deep-learning classifiers. The unlabeled data utilized in the PCB_SS model helped with the generalization of the deep-learning model and improved its performance for PCB defect detection. Thus, the proposed method alleviates the burden of the manual labeling process and provides a rapid and accurate automatic classifier for PCB inspections.

This paper describes several low‐cost methods for fabricating flexible electronic circuits on paper. The circuits comprise i) metallic wires (e.g., tin or zinc) that are deposited on the substrate by evaporation, sputtering, or airbrushing, and ii) discrete surface‐mountable electronic components that are fastened with conductive adhesive directly to the wires. These electronic circuits—like conventional printed circuit boards—can be produced with electronic components that connect on both sides of the substrate. Unlike printed circuit boards made from fiberglass, ceramics, or polyimides, however, paper can be folded and creased (repeatedly), shaped to form three‐dimensional structures, trimmed using scissors, used to wick fluids (e.g., for microfluidic applications) and disposed of by incineration. Paper‐based electronic circuits are thin and lightweight; they should be useful for applications in consumer electronics and packaging, for disposable systems for uses in the military and homeland security, for applications in medical sensing or low‐cost portable diagnostics, for paper‐based microelectromechanical systems, and for applications involving textiles.

Vision-based inspection of printed circuit board (PCB) soldering defects was studied for preparing feature data and classifying the overall PCB soldering defects on a PCB prototype into different classes. The image data of overall PCB soldering defects on a PCB prototype was developed using an image sensor camera. Image data augmentation was conducted to enhance the dataset volume. Image pre-processing included image resizing, image colour conversion, and image denoising. Watershed-based image segmentation was performed in the image post-processing to segmented images; then, feature extraction was conducted using curvelet transform to prepare image feature data. The feature data as the statistical data include kurtosis, contrast, energy, homogeneity, and variance. These data were analysed, and the percentage difference of mean values of statistical data between image classes was calculated. Kurtosis had the highest percentage difference among the statistical data. In the comparison of the mean values, kurtosis obtained 4.97% difference for the class of good and medium condition; 17.02% difference for the good and bad condition; and 12.08% difference for the bad and medium condition. Through this analysis, kurtosis is considered more reliable data for the machine-learning based classification in this project. The extracted data can be applied in future studies to classify overall solder joint defects on a PCB prototype by artificial neural network in machine learning classification.

Printing optical waveguides is an approach to the high volume implementation of optical data transmission in conventional electronic systems. Flexographic printing enables the manufacturing of circular segment-shaped polymer waveguides on planar substrates, which show great potential as economic Gbit/s-capable short-range networks. This work describes a process chain to manufacture and integrate a printed optical data transmission path in conventional printed circuit boards (PCB). This sequence of processes gives an outlook on up-scaling utilizing printed optical waveguides to mass manufacturing. Since the significant challenge in integration is achieving sufficient optical coupling, geometrical tolerances are investigated using raytracing simulation. Relevant degrees of freedom of the laser diode and waveguide are varied and validated by measuring alignment profiles. As a result, the mechanical interface provided by the PCB is presented and validated by confocal measurements. An innovative pick and place tool assembles the separated flexible waveguide to realize a demonstration system. As a validation, Fast Ethernet data transmission is presented over a flexible optical connection. In further steps, a miniaturization of the system is the goal to achieve a standardized system for applications like galvanic isolation.

The amount of data in the field of computer networking is growing rapidly and this urges new challenges in the field of an intrusion detection system (IDS). To handle such increasing volume of data, a new hybrid approach has to be developed to overcome the problems such as high detection rate and low false alarm rate. An intrusion detection system plays a vital role in the detection of malicious attacks. Data mining and machine learning techniques are important and play a vital role in the detection of attacks. This paper mainly focuses on detection rate and false alarm rate and so to resolve these problems a hybrid method, ensemble clustering, has been proposed. This method tries to increase detection rate with lowering false alarm rate. The method has been tested on KDDCup'99 network intrusion dataset and performs well as compared with other algorithms in terms of detection rate and false alarm rate.

Mass via arrays (MVAs) are intersubstrate thermal management structures that utilize thermal meta-material design principles to target localized hot spots and extreme variation in the temperature profile of electronic systems. MVAs have shown promise for integration into electronic systems as passive thermal management techniques. Theoretical analysis has shown that, when properly designed, MVAs and MVA-like structures provide control over how the heat is transferred in an electronic substrate. While the theoretical confirmation of this behavior is promising, experimental results are important to prove and strengthen MVA design principles. In this work, MVAs are implemented using an industry-standard printed circuit board (PCB) fabrication technique with Rogers 4350B (RO4350) material. The design structures are first theoretically modeled using a multilayer RO4350 stack-up in which equivalent thermal properties are studied for a variety of MVA designs. Uncertainty metrics are integrated into this model, and an iterative, Monte Carlo process is used to simulate variability in MVA performance. Next, these theoretical structures are implemented in conventional PCBs. Sample devices are chosen at random, and the heat spreading characteristics of the devices are measured using a thermal imaging camera. The results of these measurements confirm the theoretical baseline that an MVA structure provides improved thermal management characteristics relative to conventional thermal via array (TVA) structures.