Autovesk: Automatic Vectorized Code Generation from Unstructured Static Kernels Using Graph Transformations

GPUs provide high-bandwidth/low-latency on-chip shared memory and L1 cache to efficiently service a large number of concurrent memory requests. Specifically, concurrent memory requests accessing contiguous memory space are coalesced into warp-wide accesses. To support such large accesses to L1 cache with low latency, the size of L1 cache line is no smaller than that of warp-wide accesses. However, such L1 cache architecture cannot always be efficiently utilized when applications generate many memory requests with irregular access patterns especially due to branch and memory divergences that make requests uncoalesced and small. Furthermore, unlike L1 cache, the shared memory of GPUs is not often used in many applications, which essentially depends on programmers. In this article, we propose Elastic-Cache, which can efficiently support both fine- and coarse-grained L1 cache line management for applications with both regular and irregular memory access patterns to improve the L1 cache efficiency. Specifically, it can store 32- or 64-byte words in non-contiguous memory space to a single 128-byte cache line. Furthermore, it neither requires an extra memory structure nor reduces the capacity of L1 cache for tag storage, since it stores auxiliary tags for fine-grained L1 cache line managements in the shared memory space that is not fully used in many applications. To improve the bandwidth utilization of L1 cache with Elastic-Cache for fine-grained accesses, we further propose Elastic-Plus to issue 32-byte memory requests in parallel, which can reduce the processing latency of memory instructions and improve the throughput of GPUs. Our experiment result shows that Elastic-Cache improves the geometric-mean performance of applications with irregular memory access patterns by 104% without degrading the performance of applications with regular memory access patterns. Elastic-Plus outperforms Elastic-Cache and improves the performance of applications with irregular memory access patterns by 131%.

Sparse Matrix-Vector Multiplication (SpMV) is the most important sparse linear algebra kernel in both scientific and engineering applications. Due to its irregular control flow and data access pattern, Von Neumann architectures like CPUs and GPUs cannot fully exploit the inherent parallelism of S pMV. Although FPGAs can efficiently accelerate SpMV in a dataflow manner, their performance is degraded in face of large matrices that exceed the capacity of on-chip memory because of excessive rescheduling of data. In this paper we propose ReDESK, a Reconfigurable Dataflow Engine for Sparse Kernels, for emerging tightly-coupled CPU-FPGA heterogeneous platforms. To fully exploit the heterogeneity, we design a novel representation of sparse matrix that is tailored for data prefetching on CPU-side and streaming processing on FPGA-side. In this way ReDESK can fully utilize the memory bandwidth regardless of the scale of SpMV problem. We evaluate ReDESK on Intel HARP-2 platform with a set of matrices from the University of Florida sparse matrix collection. The result demonstrates an average bandwidth utilization of 0.094 GFLOP/GB, which is 1.6-4.3x more efficient than previous SpMV on FPGAs.

We are going through the computation from single core to multicore architecture in parallel programming. Graphics Pro- cessor Units (GPUs) have recently emerged as outstanding platforms for data parallel applications with regular data access patterns. However, it is still challenging to optimize computations with irregular data access patterns like sparse matrix-vector multiplication (SPMV). SPMV is one of the most important computational kernels in engineering practice and scientific computation. Various data formats to store the sparse matrix have been implemented on GPUs to maximize the performance. In this paper, we propose and evalu- ate a new implementation of SPMV on GPU based on QCSR storage format which combines the quadtree storage format and CSR format. We also outline some optimization strategies to improve performance. In comparison with previously published implementa- tion, it achieves higher overall performance than BCSR format. The results show that it achieves 1.15 speedup averagely than BCSR format.

The low-code approach is an important area of research being developed to improve the rapid creation and performance of software applications. This approach allows developers and users to easily create software applications through an interactive interface. Existing research shows that the low-code approach accelerates the development process in innovative ways, saves effort and time, and reduces code complexity. This study analyses and compares automatic code generation and transformation techniques in low-code platforms. The study analyses the contributions of automatic code generation and transformation to software engineering processes and evaluates the impact of these techniques on software product quality and development speed. The importance of the Model-Based Development (MBD) approach in automated code generation processes is highlighted. It is stated that MBD provides benefits such as speeding up the software development process and reducing errors by enabling automatic code generation from high-level abstract models. In the study, various literature studies were evaluated to examine the impact of automatic code generation and transformation techniques on the application development process. These studies have shown how automatic code generation and transformation techniques are applied, what results are achieved and what contributions these techniques make to the software development process. The results of the study show that automatic code generation and transformation techniques have a great impact on the application development process. In particular, the acceleration of the software development process, the reduction of errors and the ability to produce more effective and efficient software products are important benefits of these techniques. In addition, it has been found that this approach increases the success of software projects by enabling software developers to produce fast and accurate solutions in complex systems. In this context, the importance of automatic code generation and transformation techniques plays an important role in software development processes.

Locality analysis of an application helps us extract data access patterns and predict runtime cache behavior. In this paper, we propose a locality-aware dynamic mapping algorithm for multithreaded applications, which assigns computations with similar data access patterns to same cores. We collect the amounts of shared and distinct data used by all computations, called chunks and calculate sharing among those chunks. Then, chunks with the similar data access patterns are grouped into bins, which are subsequently assigned to threads for improving cache reuse and program performance. Our algorithm is illustrated with sparse matrix-vector multiply (SpMV), which is one of the most widely used kernel in engineering and scientific computing and suffers from irregular and indirect memory access patterns. Five inputs with different shapes and characteristics are considered for testing the performance of our algorithm. Based on the results of experimental study, our algorithm outperforms Linux scheduler with an average of 12.5% performance improvement for various scenarios considered.

High-performance computing (HPC) has enabled advancements in computation speed and resource cost by utilizing all available server resources and using parallelization for speedup. This computation scheme encourages simulation model development, massive data collection, and AI computation models, all which store and compute on massive amounts of data. Data compression has enhanced the performance of storing and transferring this HPC application data to enable acceleration, but the benefits of data compression can also be transferred to the active allocated memory used by the application. In-line compression is a compression method that keeps the application memory compressed in allocated memory, decompressing memory as its data is needed by the algorithm. The actively decompressed data size in allocated memory can be limited by grouping and compressing the data into blocks informed by the application's computational kernel's data access patterns and a selected compressor. This research explores factors such as block size and compressor choice on the runtime and memory usage of the Matrix Multiplication kernel. Matrix multiplication (MM) is a fundamental HPC algorithm that exemplifies the memory access patterns and use cases present in other HPC kernels. MM kernels provide a baseline for evaluating in-line compression due to MM's row-based data access patterns and the usage of several matrices to compute the resulting matrix. Trade-offs between memory size and the compression runtime necessitate tuned parameters for each in-line compression-enabled kernel. The results of this research demonstrate essential parameter trends, trade-offs, and the importance of locality in the kernel's data access patterns.

Application of vector and parallel supercomputers to ground-water flow modeling

The digital signal processing (DSP) processor-in-the-loop tests based on automatic code generation technology are studied. Firstly, the idea of model-based design is introduced, and the principle and method of embedded code automatic generation technology are analyzed by taking the automatic code generation of the DSP control algorithm for pulse width modulation (PWM) output as an example. Then, the control system model is established on MATLAB/Simulink. After verifying the model through simulation, the target board platform is established with DSP as the core processor, and the automatically generated code is tested by the processor-in-the-loop (PIL). The results show that the technology greatly shortens the development cycle of the project, improves the robustness and consistency of the control code, and can be widely used in the complex algorithm development process of the controller, from intelligent design and modeling to implementation.

Automatic code generation for production automotive powertrain applications introduces many challenges for the tool vendor. Resource efficiency, reliability, and product process development issues need to be addressed. Automatic code generation used for rapid prototyping systems usually will not satisfy the requirements necessary for production oriented code generation. Some of the requirements critical to automatic code generation are not immediately obvious to a tool vendor who is not active in the user's industry. The purpose of this paper is to address some of the most common requirements for production automotive powertrain code generation.

Loop vectorization remains a challenging task. While automatic vectorization from compilers can now handle a wide range of codes, the underlying dependency reasoning tends to fail when either data or control flow become too complex. Guided vectorization as, e. g., provided by OpenMP pragmas, allows the compiler to offload the reasoning to the developer and handle more code in turn. However, neither guided nor automatic vectorization has yet been able to generate suitable data structures for vectorized code. In this case, explicit vectorization remains the sole option for programmers. We present our general-purpose approach to explicitly vectorize complex loops based on C++ templates and the upcoming std::simd library. The core idea of this approach is the introduction of a SIMD index type, which allows loop bodies to be completely written in a simd-generic way. On top of that, we have developed the open source library SIMD_ACCESS, which complements std::simd. This library adds streamlined load and store expressions, residual and aligning loop handling and a framework for vectorizing data structures. We conclude the paper with a performance evaluation. We show that there is no performance overhead caused by our abstraction layer. Finally, we investigate and compare two different vectorization approaches of a loop in a Discontinous-Galerkin Spectral-Element Method in an industry-grade CFD code for unstructured meshes.

Applications that exhibit regular memory access patterns usually benefit transparently from hardware prefetchers that bring data into the fast on-chip cache just before it is required, thereby avoiding expensive cache misses. Unfortunately, unstructured mesh applications contain irregular access patterns that are often more difficult to identify in hardware. An alternative for such workloads is software prefetching, where special non-blocking instructions load data into the cache hierarchy. However, there are currently few examples in the literature on how to incorporate such software prefetches into existing applications with positive results. This paper addresses these issues by demonstrating the utility and implementation of software prefetching in an unstructured finite volume CFD code of representative size and complexity to an industrial application and across a number of processors. We present the benefits of auto-tuning for finding the optimal prefetch distance values across different computational kernels and architectures and demonstrate the importance of choosing the right prefetch destination across the available cache levels for best performance. We discuss the impact of the data layout on the number of prefetch instructions required in kernels with indirect-access patterns and show how to integrate them on top of existing optimisations such as vectorisation. Through this we show significant full application speed-ups on a range of processors, such as the Intel Xeon Skylake CPU (15%) as well as on the in-order Intel Xeon Phi Knights Corner (1.99x) architecture and the out-of-order Knights Landing (33%) many-core processor.

Operations that combine smaller networks into a larger network in a manner such that the rate region of the larger network can be directly obtained from the associated rate regions of the smaller networks are defined and presented. The operations are selected to also have the property that the sufficiency of classes of linear network codes and the tightness of the Shannon (polymatroid) outer bound are preserved in the combination. Four such operations are defined, and the classes of linear codes considered include both scalar and vector codes. It is demonstrated that these operations enable one to obtain rate regions for networks of arbitrary size, and to also determine if some classes of linear codes are sufficient and/or the Shannon outer bound bound is tight for these networks.

The development of avionics software demands more and more human intervention. The software development process is rather highly expensive and risky since it must undergo certification. Automation of such a process can reduce errors and human interaction. Automated development tools usually deal with automatic code generation. These approaches are actually based on pre-defined fixed rules and policies to automatically generate software code which still demands considerable hand-coded software. This paper presents a self-directed development process that is able to make decisions by its own to generate software code. The automated decision-making process relies on a reasoner, and an ontological database that captures development skills from human developers as well as the dynamic configurations and capabilities of the system under development. The knowledge captured enables highlevel reasoning to automatically generate the control software code. A case study based on the development of Embedded Control Software (ECS) for Distributed Aircraft Fuel Management (DAFM) is presented. Details of the reasoning ontology to develop ECS, and experimental results from ECS for DAFM automatically generated are presented.

Automatic code generation has been around for a long time, and the core technologies used are constantly evolving. Around application development work in the demand for high quality code generated rapidly, this paper proposes a automatic code generation method based on sequence generative adversarial network, the method adopts the adversarial learning thought, using LSTM as a generator, CNN as a discriminator, both through against each other to generate higher quality code samples. Experiment results show that this method can generate code automatically at the second level, and is significantly better than the existing methods in terms of generation rate and accuracy, which explores a new way of automatic code generation.

This paper describes the IOPT-Tools cloud-based tool-chain, offering a complete set of tools supporting design automation for embedded controller’s development, benefiting from adopting a model-driven development attitude. The tools are freely available online at http://gres.uninova.pt/IOPT-Tools/ . The tool-chain relies on IOPT nets (Input-Output Place-Transition nets) to describe the controller behavior, allowing an explicit representation of constraints on input and output signals and events, which is necessary for the development of controllers. The IOPT-Tools tool-chain includes tools for interactive graphical IOPT nets models editing, simulation and test (token-player, timing diagram, remote debugging), as well as a state-space generator, state-space visualization, and a query system for properties verification. The tool-chain also supports the automatic generation of execution code to be directly deployed in the controllers’ implementation platforms, such as FPGA boards, as well as Arduino, Raspberry, and other Linux-based boards. Most notably, it is possible to obtain C code and VHDL code to be directly deployed into the referred boards without writing/changing a line in the generated code. The tool-chain uses the PNML format for storing the models and can import PNML models generated by other frameworks, automatically generating, if necessary, an associated graphical representation. After, it is possible to add input and output signals and events to create controller models. IOPT-Tools also supports net operations, namely net addition, allowing composition of sub-models, and net splitting, which in conjunction with the use of clock domains and dedicated communication channels support the development of distributed controllers.