Backgate Modulation Technique for Higher Efficiency Envelope Tracking

This paper investigates the trade-off between power amplifier (PA) nonlinearity, output power backoff (OBO), digital predistortion (DPD), and clipping and filtering (CF) in terms of energy consumption. The energy efficiency of a PA depends on the OBO of the signal and usually increases as the OBO decreases. Peak to average power ratio (PAPR) reduction methods like CF and PA linearization algorithms like DPD methods allow the use of a smaller OBO. Those algorithms show best results when used together. By studying the trade-off between the power consumed in the CF and DPD circuits versus having a larger OBO for a target bit-error rate (BER), we show that below a certain PA output power the power consumption is not reduced by decreasing the OBO. We also show that the increase in distortion noise when using DPD and CF might defeat the purpose of their use in terms of power consumption. Given the trend toward smaller cells like femtocells, requiring less output power, CF and DPD may not be required at all, leading to a simpler and power saving transmitter design.

In this work, a new particle swarm optimization (PSO) method with dynamic nonlinear self-adaptive hyperparameters (DNSHs) (PSO-DNSHs) is proposed for radio frequency (RF) power amplifier (PA) design. The theory and advantages of this method are described and analyzed. Based on the proposed PSO-DNSH method, a multioctave PA and a broadband pseudo-Doherty load-modulation balance amplifier (PD-LMBA) are designed. The multioctave single-ended PA achieves an output power exceeding 40.3 dBm, a drain efficiency greater than 60.9%, and a gain of over 10.3 dB between 0.5 and 3.6 GHz. While the broadband PD-LMBA shows a saturated output power of 41.1–43 dBm, a saturation drain efficiency of 57.7%–77.6%, a 6-dB output power back-off (OBO) DE of 47.3%–64.6%, and a 10-dB OBO DE of 51.2%–68.4%. Compared with other existing PSO-based methods, the results demonstrate that the proposed method not only achieves better performance for both PAs, but also shows faster convergence capability. Modulated signal tests along with the digital predistortion (DPD) are also conducted for both PAs, 20-MHz 5G new radio (NR) signal with 6- and 10-dB peak-to-average power ratios (PAPRs) are used for single-ended PA and PD-LMBA, respectively. Excellent linearity is achieved for both PAs.

This article presents the analysis and design of a three-stage load modulated power amplifier (PA), in which three amplifiers, each with different biasing, are connected to a four-port coupler. It is illustrated that, by properly configuring current relationships between the three amplifiers, this new load modulated PA can provide flexible output power back-off (OBO) and achieve high efficiency within a large OBO range. A detailed theoretical analysis and design methodology are given. In this architecture, the OBO level can be adjusted by simply setting bias conditions of the relevant amplifiers that correspond to the current relationships. Therefore, after circuit fabrication, the OBO range can still be reconfigured without redesigning the circuit. To validate the proposed approach, a prototype operating at 3.45 GHz is demonstrated and implemented with gallium nitride (GaN) transistors. The measured saturated output power reaches 45 dBm with 70.1% drain efficiency. At 6-/8-/10-dB OBO, the fabricated PA can provide up to 62.1%/53.8%/47.3% drain efficiency, respectively. When driven by a 60-MHz 9-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal, the PA provides 34-dBm average output power with 44.3% average efficiency. Moreover, measurement results prove that the PA can offer efficiency enhancement when the OBO is reconfigured to 8 or 12 dB after fabrication.

In the recent years, there has been an increased focus on RF power amplifiers for communications especially for wireless applications. The main reasons of focus include high integration of power amplifier and low cost of production. To be able to reach the goal some theory on RF power amplifiers is necessary. The different classes of operation are explained, then the principles of impedance matching is discussed. This includes the development of the simulated load-pull method and synthesis of impedance matching networks. Then the biasing of the power amplifier is discussed along with the stability issues. RF power amplifier designing, simulation and implementation at 5MHz is described in this thesis. The issues of modeling a complete power amplifier are treated. This includes modeling of the circuit, the passive devices on-chip and off-chip as well as the package and PCB. To ease the design of power amplifier a design method is developed based on the theory and the experimental work. At last the experimental work is described. The first part is a linearization system based on simulation. Then the RF power amplifier designed during the project are introduced. The power amplifier shows superior performance when at its operating frequency 5MHz. The output power of this power amplifier is 50.419dB. The power amplifier utilizes the design method develop as well as the models described. The accurate modeling combined with superior performance proves the future of integrated RF power amplifiers for wireless communication.

Most existing behavioral models of the radio frequency (RF) power amplifiers assume that power amplifiers are memoryless devices. But in broadband communication systems, memory effects of the RF power amplifiers are significantly observed. The traditional memoryless models can no longer accurately depict the input-output relationship of power amplifiers. This paper investigates power amplifiers memory effects and a pre-distortion method is proposed for linearizing RF power amplifiers with memory effects. A valid behavioral model based on the Volterra series is suggested to treat memory effects. Since the characteristics of amplifiers change during transmission time, a recursive least squares algorithm with size- fixed observation matrices is developed to update the parameters of the proposed power amplifiers model. The identification algorithm can decrease computational complexity and data storage space and facilitate real-time online identification. Simultaneously, the pre-distortion model is constructed to simulate. Simulation results show that the proposed method can effectively compensate for the nonlinear distortion and memory effects of RF power amplifiers. The model's accuracy is used to evaluate power amplifiers memory effects by the enormalized mean square error (NMSE). In the end, simulation and evaluation of this pre-distortion system proceeded, and the power spectral density estimation was also applied to calculate the adjacent channel power ratio.

Envelope tracking (ET) is a key technology improving efficiency of RF power amplifiers (PAs) and battery lifetime in mobile handsets. It has been commercialized since 4G LTE era, and is also being employed in 5G NR handsets. A supply modulator (SM) is a circuit generating power supplies of RF PAs for ET and average power tracking (APT) operations. Currently, the maximum channel BW and supported ET BW of 5G NR handset is 100MHz [1]–[4]. In a short time, over 100MHz BW will be necessary to support intra-band contiguous carrier aggregation cases of n77C/n78C/n79C in 3GPP standard [5]. The required instantaneous maximum output power of SM is about 10W which is calculated by the following parameters: 26dBm output power by power class 2 (PC2), 2dB loss of RF front-end module (FEM) due to complex operating band combinations (EN-DC for non-standalone mode, NE-DC, 2CA/3CA), 6dB higher instantaneous power due to peak-to-average power ratio (PAPR) at 1 resource block (RB), 1dB margin, and poor PA efficiency of around 33% (worst example) due to high carrier frequency of 5GHz at n79 band. The poor PA efficiency can be relaxed by high voltage PA design beyond 5V. In [1], a supply modulator with boosted output larger than battery voltage $(V_{BAT})$ is proposed, and the designed PA with 30% higher voltage shows 10% higher efficiency and broader BW owing to low impedance transformation ratio from $50 \Omega$ and small parasitic output capacitance of power cell. The challenge is how to design a supply modulator for 5G NR that can achieve both wide ET BW and high output voltage/power capability, while satisfying high efficiency, low receiver-band noise, short transition time, and multi-mode/standard operation.

<?Pub Dtl=""?> This paper presents a linear multi-harmonic analysis method to evaluate the performance of digitally controlled dual RF-input power amplifiers (PAs). The method enables, due to its low computational cost, optimization of PA efficiency and bandwidth in a complex design space involving two independent inputs. Under the idealized assumption of short-circuited higher harmonics, the analysis is used to prove the existence of a Doherty-outphasing continuum, featuring high average efficiency over 100% fractional bandwidth. With this result as a foundation, a combiner incorporating microwave transistor parasitics is analyzed without assuming short-circuited higher harmonics, showing that high average efficiencies are also achievable under more realistic conditions. A PA is straightforwardly designed from these calculation results using two 15-W GaN HEMTs. The simulated layout-ready (large-signal transistor model) PA average drain efficiency exceeds 50% over 1.1–3.7 GHz for a 6.7-dB peak-to-average power-ratio WCDMA signal. The measured PA has a maximum output power of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox{44}} \pm {\hbox{0.9}}$</tex></formula> dBm and a 6-dB output power back-off (OPBO) power-added efficiency (PAE) of 45% over 1–3 GHz. After applying digital pre-distortion, excellent linearity is demonstrated when transmitting the WCDMA signal, resulting in an adjacent channel leakage power ratio lower than <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}{\hbox{57}}$</tex></formula> dBc with corresponding average PAE of 50% and 40% at 1.2 and 2.3 GHz, respectively. This is, to the authors' knowledge, the most wideband OPBO efficiency enhanced PA reported to date, proving the effectiveness of employing linear multi-harmonic analysis in dual-input PA design.

A CMOS class-E outphasing RF power amplifier is presented with a new passive combining circuit that provides high efficiency and high output power. An efficiency enhancement circuit and a power enhancement circuit are proposed as part of the combiner that improve efficiency at power back-off and increase output power without violating reliability limits, respectively. The proposed power amplifier is designed in a 45nm CMOS technology. The power amplifier (PA) delivers 29.5 dBm peak output power at 2.4 GHz with 46.76% drain efficiency at peak output power, 32.96% drain efficiency at 3 dB power back-off, and 21.16% drain efficiency at 6 dB power back-off. The proposed power amplifier shows excellent linearity with digital pre-distortion. Better than -50 dBc adjacent channel power ratio (ACPR) is obtained with 64-QAM long-term evolution (LTE) signal with 10 MHz and 20 MHz bandwidth. For two-carrier 20 MHz LTE signal, -44 dBc ACPR is achieved. 21% average drain efficiency is obtained with LTE signal with a 6 dB peak-to-average power ratio. The PA is also tested with 802.11g WLAN signal and it satisfies the spectral mask requirement with high margin. 1.4% (-37.1 dB) error vector magnitude (EVM) is obtained with LTE signal (64-QAM) with a 10 MHz bandwidth.

In this paper, a quasi-asymmetric Doherty power amplifier (PA) is designed without load modulation using the GaAs 0.25 µm pHEMT technology to reach an enlarged output power back-off (OPBO) with circuitry solutions in order to overcome technology restrictions. To prevent power leakage in auxiliary PA (PAaux) due to its extremely low off-state impedance (Zoff), a Wilkinson power combiner is added to the output. Moreover, an input asymmetric power divider is designed to guarantee that no considerable power is delivered to the main PA (PAmain) in the high-power region to make it saturated. A two-section matching network is proposed for PAmain, which simultaneously compensates for phase differences of the main and auxiliary amplification paths. To control the significant impedance variation of PAaux versus sweeping power and the different impedance trajectories of the main and auxiliary amplification paths, the bias and dimension selection of PAaux are analyzed to reach the desired output power profile versus input power. These methods overcome impedance variations and linearity degradation. To achieve the aimed 10% fractional bandwidth, appropriate low-quality LC-networks are selected as matching networks. The simulation results indicate the utility of the proposed structure for microwave link applications. Continuous-wave simulations imply that the proposed PA has a 33 dBm maximum output power and a 13.5 dB power gain with less than 1 dB power gain compression in the desired frequency range (7.6–8.4 GHz). The drain efficiency of 30% at the highest input power, minimum of second and third harmonic powers of − 140 dBm and − 130 dBm, respectively, and OPBO of 7.5 dB are also obtained.

A cascode configuration in class-E CMOS power amplifiers (PAs) provides high reliability with respect to breakdown considerations. However, it causes a power loss due to the slow transition of a common-gate device from the triode region to the cut-off region. To minimize the power loss of cascode class-E CMOS PAs, we propose a charging acceleration technique, CAT. This method incorporates a capacitive element between the drain and the source of a common-gate device in a cascode configuration, accelerating the charging speed responsible for turning off a common-gate device instantly after a common-source device is turned off and thus minimizing power loss from the device. We compared the performance of the proposed cascode class-E PA to that of the conventional cascode class-E PA using a 0.18- CMOS process. With a 3.3-V power supply, the proposed fully-integrated CMOS PA achieves 30.7 dBm of maximum output power and 45.6% of power-added efficiency (PAE) with a dynamic range of 40 dB at 1.6 GHz. According to measurements, the proposed cascode class-E PA shows improvement in PAE over the conventional class-E PA of between 5% and 9% in a 1.5 to 2.0 GHz range.

Turkish accelerator and radiation laboratory (TARLA) is an accelerator based oscillator mode free electronlaser (FEL) facility under construction. The acceleration beamline includes a fundamental buncher (FB) in order to confine the electron beam into a compressed bunch. In this study, we demonstrate the commissioning tests of 500 W RF amplifier powering FB and present the phase stability dependence on the pressure and temperature of the water cooling line under long time run conditions.As the disturbing effects break down the synchronization between the particle and RF power during acceleration, the reasons disquieting the stability of the RF amplifier are investigated. One reason which causes disturbance in the stability is the variation in the phase of the output power. Phase variation of the output power of the RF amplifier which was measured as $\sim$10 deg/$^{\circ}$C in average initially, which was beyond permitted variation levels by the controller electronics, namely the low level RF system (LLRF), is decreased to less than $\sim$0.45 deg/$^{\circ}$C by incorporating a phase shifter. In addition, this phase variation reduction is accompanied with a reflected power at the output of the RF amplifier decline from 4.3 W (~36.33 dBm) down to 3 mW (~4.7 dBm) by utilizing a circulator, which is also important and desirable in terms of protection of the electronics in the long term run. As ensuring phase stability in the output power is very important, this work may serve as a guide since the documentation regarding the output power dependence of the water cooling line for long term run is very limited.

This paper presents an innovative stacked-FET cell useful to enhance both, gain and output power of RF and mm-wave power amplifiers. The new structure has been validated through the design of a downlink Ka-band Doherty Power Amplifier. The resulting module is a two stages Microwave Monolithic Integrated Circuit (MMIC) fabricated on a commercial 100nm gate length Gallium nitride on Silicon technology. The design was carried out to satisfy not only the power requirements but also to meet the thermal constraints for space use. Simulation results have shown a power added efficiency (PAE) greater of 30% at 6dB of output power back-off with a peak of output power of 38dBm inside the operative band, from 17.3 GHz to 20.3 GHz. Whereas, a saturated gain above 17dB has been achieved with a gain flatness better than 0.5dB in the overall band. The chip area is 5×3.7mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper presents a novel power combining architecture, referred to as distributed efficient power amplifier (DEPA) that mitigates the inherent bandwidth limiting factors in a Doherty power amplifier (DPA), namely, impedance inversion and load modulation, by distributing the conventional auxiliary amplifier of the DPA to multiple auxiliary subamplifiers along a broadband multisection impedance transformer. The proposed technique is demonstrated through the design, implementation, and measurement of a wideband DEPA having 8-dB output power back-off and 72% fractional bandwidth. The experimental results show a Doherty-like efficiency enhancement from 1.8 to 3.8 GHz. For the output power levels of 37.4±1.1 and 45.4±1.1 dBm, corresponding to 8-dB OBO and peak output power, the efficiency levels are between 41%-51% and 42%-62%, respectively. Furthermore, linearized modulated measurements show that the DEPA is linearizable and meets the spectral requirements for modern wireless communication systems.

This paper presents the effects of defected ground structure (DGS) on different ground planes in RF power amplifiers (PAs). Two DGS patterns etched on the front and back planes of printed circuit board which are named Top-DGS and Bottom-DGS, and a thru microstrip line are manufactured and measured to compare the insert loss at the fundamental and second harmonic frequencies. In order to evaluate the effects of the Top-DGS, Bottom-DGS and without DGS on the PA, three 4W PA have been designed and measured. Measured results show that the PA with the Top-DGS can reject the second harmonic about 13dB at Pout 34.76dBm, and achieve better the output power (Pout) and power added efficiency (PAE) than the one without DGS; the one with the Bottom-DGS has the suppression of about 28dB for the second harmonic at Pout 34.21dBm, and has less the Pout and PAE for the decreased characteristic impedance (Z <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</inf> ) of DGS pattern.

A 10 watt radio frequency power amplifier using commercially available silicon carbide (SiC) metal semiconductor field effect transistors (MESFETs), Cree CRF‐24010F, was designed. The frequency range covers 5.15 GHz to 5.35 GHz for using IEEE 802.11a Wireless Local Area Network (WLAN) applications. The 2nd and 3rd order harmonics cancellation technique was introduced to obtain high linearity. A cascade topology was employed to increase small signal gain, isolation, and stability throughout the bandwidth. At VDS1 = VDS2 = 48 V and IDS1 + IDS2 = 871 mA, 11 ± 1 dB power gain, 40 dBm (10 W) output power and 32.5% power added efficiency (PAE) over the operating bandwidth have been achieved in the two stage design. Two‐tone simulation at frequency spacing of 10 MHz was also done and output 3rd order intercept point (OIP3) of 49 dBm was obtained. (© 2008 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)