Bandwidth-enhanced photopolymer waveguide hologram-based optical backplane

On-chip communication architecture plays an important role in determining the overall performance of the System-on-Chip (SoC) design. In the recourse sharing mechanism of SoC, the communication architecture should be flexible to offer high performance over a wide range of traffic. The paper describes and evaluates the use of fuzzy logic arbiters for shared-bus multiprocessor system. In such systems, arbiters are used to resolve conflicts between processor requests shared bus. Typically, these conflicts are resolved by using two-stage arbitration schemes that employ policies such as random choice, daisy chaining, round-robin, etc. A new way of implementing these arbiters is the use of fuzzy logic to resolve resource request conflicts based on the system state and performance variables. This paper proposed a new technique for implementation of fuzzy logic in the system arbiters and presents a simulation program. The inputs are fuzzified by using appropriate membership functions, and rules have been defined in such a way as to increase and distribute evenly the acceptance rate of each processor in the system

Since the invention of the transistor, clock frequency increase was the primary method of improving computing performance. As the reach of Moore's law came to an end, however, technology driven performance gains became increasingly harder to achieve, and the research community was forced to come up with innovative system architectures. Today increasing parallelism is the primary method of improving performance: single processors are being replaced by multiprocessor systems and multicore architectures. The challenge faced by computer architects is to increase performance while limited by cost and power consumption. The appearance of cheap and fast interconnection networks has promoted designs based on distributed memory computing. Most modern massively parallel computers, as reflected by the Top 500 list, are clusters of workstations using commodity processors connected by high speed interconnects. Today's massively parallel systems consist of hundreds of thousands of processors. Software technology to program these large systems is still in its infancy. Optimizing communication has become a key to overall system performance. To cope with the increasing burden of communication, the following methods have been explored: (i) Scalability in the messaging system: The messaging system itself needs to scale up to the 100K processor range. (ii) Scalable algorithms reducing communication: As the machine grows in size the amount of communication also increases, and the resulting overhead negatively impacts performance. New programming models and algorithms allow programmers to better exploit locality and reduce communication. (iii) Speed up communication: reducing and hiding communication latency, and improving bandwidth. Following the three items described above, this thesis contributes to the improvement of the communication system (i) by proposing a scalable memory management of the communication system, that guarantees the correct reception of data and control-data, (ii) by proposing a language extension that allows programmers to better exploit data locality to reduce inter-node communication, and (iii) by presenting and evaluating a cache of remote addresses that aims to reduce control-data and exploit the RDMA native network capabilities, resulting in latency reduction and better overlap of communication and computation. Our contributions are analyzed in two different parallel programming models: Message Passing Interface (MPI) and Unified Parallel C (UPC). Many different programing models exist today, and the programmer usually needs to choose one or another depending on the problem and the machine architecture. MPI has been chosen because it is the de facto standard for parallel programming in distributed memory machines. UPC was considered because it constitutes a promising easy-to-use approach to parallelism. Since parallelism is everywhere, programmability is becoming important and languages such as UPC are gaining attention as a potential future of high performance computing. Concerning the communication system, the languages chosen are relevant because, while MPI offers two-sided communication, UPC relays on a one-sided communication model. This difference potentially influences the communication system requirements of the language. These requirements as well as our contributions are analyzed and discussed for both programming models and we state whether they apply to both programming models.

With the advent of optical fiber and other advanced technologies in solid state, pipelining signals at the wire (or transmission line) level has become possible. this has, in turn, made the slotted bus a potential candidate for interconnection networks (IN) for tightly coupled multiprocessor systems. However, a bus can provide only limited bandwidth. Though slotted bus can provide considerably more bandwidth in comparison to the traditional non-slotted bus, it is not enough for fine-grain parallel applications run on the shared-memory systems. One well known method to increase the effective bandwidth of a slotted bus in the LAN/MAN environment is to reuse the bandwidth by reusing slots. However, in a tightly coupled environment reusing slots is not a lucrative option because the significant buffering needs arising from slot reuse will introduce intolerable delay. In this paper we propose a methodology to reuse part of the bandwidth available from temporal and spectral bandwidth expansion with none or minimum buffering delay, resulting in significant performance improvement inboth the effective throughput and response time (communication latency). The proposed method entails the design and analysis of a re-configurable bus structure with both temporal and spectral bandwidth expansion and a polynomial time algorithm for optimal configurations for given traffic conditions. We have compared the performance of our reconfigured bus with that of the traditional slotted bus for uniform and localized traffic pattern and found that the reconfigured bus outperforms the traditional slotted bus substantially in many practical scenarios.

This simulation-based study examines the behavior of a realistic shared-memory multiprocessor system that utilizes Omega networks. A unique aspect is the presence of bursts of requests, such as processors with associated vector units or caches would generate. It is demonstrated that the forward network, the memory modules, and the reverse network of such a system interact and affect each other’s performance such that good performance depends less on the speed of any one component than on the interaction between them. Cost-effective modifications for improving this balance are evaluated. Within the range of system sizes studied (32 to 512 processors), results show that MIN-based systems that operate close to their peak memory bandwidth can indeed be constructed.

With the growing demand for data center interconnect (DCI) capacity, partial response equalization (PRE), employing either a 1/(1+D) decoder or an maximum likelihood sequence estimation (MLSE) decoder, has emerged as an effective solution to address the critical bandwidth limitations restricting system transmission rates. However, the 1/(1+D) decoder suffers from its inherent feedback loop and error propagation, while the MLSE decoder is limited by its high hardware complexity. Meanwhile, blind adaptive algorithms also encounter bottlenecks in PRE. Severe bandwidth limitations significantly impact the blind convergence of the decision-directed least mean squares (DD-LMS) algorithm. Additionally, PRE adversely affect the traditional zero forcing (ZF) algorithm, leading to extended convergence times. In this paper, we propose and experimentally demonstrate a hardware implementable PRE with reduced-state sequence estimation (RSSE) decoder and delay-ZF algorithm in a real-time 80 Gbps four-level pulse amplitude modulation (PAM- 4) intensity modulation/direct detection (IM/DD) transmission system based on an FPGA chip. Statistical results from various transmission scenarios indicate that the RSSE decoder achieves BER performance comparable to that of the full-state MLSE decoder, while reducing the implementation complexity by up to 75%. Moreover, experimental results demonstrate that under blind equalization, employing the delay-ZF algorithm to update the PAM-7 targeted FFE reduces the blind convergence time by up to 55.8% and 74.9% compared to the traditional ZF and DD-LMS algorithms, respectively.

The author presents strategies for static loop decomposition and scheduling as well as computer-assisted run-time scheduling that take into account, in addition to the cost of performing operations, the overhead costs associated with a decomposition and schedule. An algorithm for static decomposition of multidimensional loops based on the operation execution costs, communication costs, and synchronization costs is discussed. Synchronization instructions are introduced to ensure correct program execution following program decomposition. An algorithm for determining the explicit synchronization instruction that should be introduced to ensure correct execution of a program with arbitrarily nested loops is presented. Techniques for reducing run-time scheduling and communication and synchronization costs due to self-scheduling of multidimensional loops are also presented. Experiments performed on the Encore multiprocessor system demonstrate that the techniques developed can reduce overhead costs. >

Large-scale MIN-based shared-memory multiprocessor systems have long shared memory latency. Private caches can improve memory access latency but they may suf fer from the cache coherence problem and potentially lower data locality due to data sharing and multiproces sor scheduling. These two problems also increase shared memory load and may result in frequent memory stalls. In this paper, we evaluate the performance of memory caches, a cache memory placed in front of shared memory, in a large-scale multiprocessor system in the presence of pro cessor caches. The memory cache is shown to have good performance and scalability.

Scalability of cache coherence protocol is a key component in future shared-memory multi-core or multi-processor systems. The state space explosion is the first hurdle while applying model-checking to scalable protocols. In order to validate parameterized cache coherence protocols effectively, we present a new method of reducing the state space of parameterized systems, two-dimensional abstraction (TDA). Drawing inspiration from the design principle of parameterized systems, an abstract model of an unbounded system is constructed out of finite states. The mathematical principles underlying TDA is presented. Theoretical reasoning demonstrates that TDA is correct and sound. An example of parameterized cache coherence protocol based on MESI illustrates how to produce a much smaller abstract model by TDA. We also demonstrate the power of our method by applying it to various well-known classes of protocols. During the development of TH-1A supercomputer system, TDA was used to verify the coherence protocol in FT-1000 CPU and showed the potential advantages in reducing the verification complexity.

Processor scheduling policies for multiprocessor systems can be broadly divided into space-sharing and time-sharing policies. Space-sharing policies divide the system processors into a number of partitions and each partition is exclusively allocated to a single job. In time-sharing policies, processors are temporally shared by jobs. Several space-sharing and time-sharing policies have been proposed for small-scale shared-memory systems and require a central run queue and/or central scheduler. The central queue scheduler poses serious scalability problems for large-scale multiprocessor systems. Furthermore, space-sharing and time-sharing policies have their advantages and disadvantages. In this paper, we propose a new multiprocessor scheduling policy that eliminates contention for the central queue/scheduler. Our hierarchical scheduling policy (HSP) is a self-scheduling policy and uses a hierarchical run queue organization to facilitate processor allocation to jobs. We show that the HSP policy is considerably better than purely space-sharing and purely time-sharing policies over a wide range of system and workload parameters of interest.

Addresses the use of two latency hiding techniques, prefetching and weak consistency, for large-scale shared memory multiprocessors with compiler-controlled cache coherence management and the interaction of latency hiding techniques and network bandwidth. The performance effect of latency hiding is evaluated and compared varying the network channel bandwidth. The interaction of reads, writes and prefetches, given a limited bandwidth, is studied, and an approach to better network bandwidth utilization by limiting the number of outstanding requests in each node is investigated. Increasing network (channel) bandwidth helps both prefetching and non-prefetching systems, with the initial 2/spl times/ increase in bandwidth giving the most improvement. The use of prefetching can deliver a much larger improvement than increasing network bandwidth for a 128-processor system for some benchmarks, even with the minimal bandwidth. Controlling bandwidth utilization is shown to be important when prefetch and write request rates are high.

Performance of I/O intensive applications on a multiprocessor system depends mostly on the variety of disk access delays encountered in the I/O system. Over the years, the improvement in disk performance has taken place more slowly than the corresponding increase in processor speeds. It is therefore necessary to model I/O delays and evaluate performance benefits of moving an application to a better multiprocessor system. We perform such an analysis by measuring I/O delays for a synthesized application that uses a parallel distributed file system. The aim of this study is to evaluate the performance benefits of better disks in a multiprocessor system. We report on how the I/O performance would be affected if an application were to run on a system which would have better disks and communication links. In this study, we show a substantial improvement in the performance of an I/O system with better disks and communication links with respect to the existing system.

SPMD (single program multiple data) models and other traditional models of data parallelism provide parallelism at the processor-level. Barrier synchronization is defined at the level of processors where, when a processor arrives at the barrier point early and waits for others to arrive, no other useful work is done on that processor. Program restructuring is one way of minimizing such latencies. However, such programs tend to be error-prone and less portable. The author discusses how multithreading can be used in data parallelism to mask delays due to application irregularity or processor load imbalance. The discussion is in the context of Coir, the object-oriented runtime system for parallelism. The discussion concentrates on shared memory systems. The sample application is an LU factorization algorithm for skyline sparse matrices. The author discusses performance results on the IBM PowerPC-based symmetric multiprocessor system.

Frequent pattern mining is a fundamental data mining process which has practical applications ranging from market basket data analysis to web link analysis. In this work, we show that state-of-the-art frequent pattern mining applications are inefficient when executing on a shared memory multiprocessor system, due primarily to poor utilization of the memory hierarchy. To improve the efficiency of these applications, we explore memory performance improvements, task partitioning strategies, and task queuing models designed to maximize the scalability of pattern mining on SMP systems. Empirically, we show that the proposed strategies afford significantly improved performance. We also discuss implications of this work in light of recent trends in micro-architecture design, particularly chip multiprocessors (CMPs).

The electrical signals of the natural world behave in an essentially continuous manner. In contrast, the world of electronic design, which seeks to process these continuous or analog signals, is predominantly discrete or digital. Motivated and refined largely by the evolution of the digital computer, digital design affords the electronic design community a powerful structured and portable design methodology. Substantial improvements in the productivity of the digital designer have been realized over the past decade through the use of computer-based design automation tools which leverage the design methodology. The effectiveness of digital design and test methods and the comparative lack of same in the analog domain have made digital architectures the dominant choice of system designers. As the limits in signal power, dynamic range, signal precision, and signal bandwidth are expanded the use of continuous signal or analog design methods becomes essential. The complicated architectures of proposed mixed analog/digital circuits and the inherent complexity of the analog design process simply overwhelm the capabilities of conventional design automation methodologies.KeywordsCircuit DesignAnalog CircuitDesign ConceptualizationDifferential AmplifierSmall Signal GainThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

We investigate the parallel scaling of the GROMACS molecular dynamics code on Ethernet Beowulf clusters and what prerequisites are necessary for decent scaling even on such clusters with only limited bandwidth and high latency. GROMACS 3.3 scales well on supercomputers like the IBM p690 (Regatta) and on Linux clusters with a special interconnect like Myrinet or Infiniband. Because of the high single-node performance of GROMACS, however, on the widely used Ethernet switched clusters, the scaling typically breaks down when more than two computer nodes are involved, limiting the absolute speedup that can be gained to about 3 relative to a single-CPU run. With the LAM MPI implementation, the main scaling bottleneck is here identified to be the all-to-all communication which is required every time step. During such an all-to-all communication step, a huge amount of messages floods the network, and as a result many TCP packets are lost. We show that Ethernet flow control prevents network congestion and leads to substantial scaling improvements. For 16 CPUs, e.g., a speedup of 11 has been achieved. However, for more nodes this mechanism also fails. Having optimized an all-to-all routine, which sends the data in an ordered fashion, we show that it is possible to completely prevent packet loss for any number of multi-CPU nodes. Thus, the GROMACS scaling dramatically improves, even for switches that lack flow control. In addition, for the common HP ProCurve 2848 switch we find that for optimum all-to-all performance it is essential how the nodes are connected to the switch's ports. This is also demonstrated for the example of the Car-Parinello MD code.