Bell-basis quantum computation: A framework for intrinsic verification

Recent improvements in control of quantum systems make it seem feasible to finally build a quantum computer within a decade. While it has been shown that such a quantum computer can in principle solve certain small electronic structure problems and idealized model Hamiltonians, the highly relevant problem of directly solving a complex correlated material appears to require a prohibitive amount of resources. Here, we show that by using a hybrid quantum-classical algorithm that incorporates the power of a small quantum computer into a framework of classical embedding algorithms, the electronic structure of complex correlated materials can be efficiently tackled using a quantum computer. In our approach, the quantum computer solves a small effective quantum impurity problem that is self-consistently determined via a feedback loop between the quantum and classical computation. Use of a quantum computer enables much larger and more accurate simulations than with any known classical algorithm, and will allow many open questions in quantum materials to be resolved once a small quantum computer with around one hundred logical qubits becomes available.

The development of near-term quantum computers, referred to as Noisy Intermediate-Scale Quantum (NISQ) computers, has progressed rapidly in the past few years resulting in several quantum computers which vary in their underlying technology and physical constraints. The performance of these computers also varies from one quantum algorithm to another. To enable efficient selection of the quantum computer that provides the highest output fidelity for a given application, an accurate noise modeling of each quantum hardware is required. However, noise modeling for a given application is a complex problem because of the unknown interaction between the quantum circuit parameters and the noise parameters of NISQ devices. We propose the use of Machine Learning (ML) to model the performance of different quantum computers at the application level. The ML models predict the output fidelity of the quantum application executed on different quantum computers given their publicly available physical constraints. We use a diverse training dataset to cover the key features for application-level benchmarking of the quantum hardware. Our results obtained from different superconducting quantum devices show that our proposed ML models enable cost-effective quantum computer selection for different quantum applications with different fidelity metrics.

Simulation of the dynamics of quantum materials is emerging as a promising scientific application for noisy intermediate-scale quantum (NISQ) computers. Due to their high gate-error rates and short decoherence times, however, NISQ computers can only produce high-fidelity results for those quantum circuits smaller than some given circuit size. Dynamic simulations, therefore, pose a challenge as current algorithms produce circuits that grow in size with each subsequent time-step of the simulation. This underscores the crucial role of quantum circuit compilers to produce executable quantum circuits of minimal size, thereby maximizing the range of physical phenomena that can be studied within the NISQ fidelity budget. Here, we present two domain-specific (DS) quantum circuit compilers for the Rigetti and IBM quantum computers, specifically designed to compile circuits simulating dynamics under a special class of time-dependent Hamiltonians. The compilers outperform state-of-the-art general-purpose compilers in terms of circuit size reduction by around 25%–30% as well as wall-clock compilation time by around 40% (dependent on system size and simulation time-step). Drawing on heuristic techniques commonly used in artificial intelligence, both compilers scale well with simulation time-step and system size. Code for both compilers is open-source and packaged into a full-stack quantum simulation software with tutorials included for ease of use for future researchers wishing to perform dynamic simulations of quantum materials on quantum computers. As our DS compilers provide significant improvements in both compilation time and simulation fidelity, they provide a building block for accelerating progress toward physical quantum supremacy.

Compiling high-level quantum programs to machines that are size constrained (i.e. limited number of quantum bits) and time constrained (i.e. limited number of quantum operations) is challenging. In this paper, we present SQUARE (Strategic QUantum Ancilla REuse), a compilation infrastructure that tackles allocation and reclamation of scratch qubits (called ancilla) in modular quantum programs. At its core, SQUARE strategically performs uncomputation to create opportunities for qubit reuse. Current Noisy Intermediate-Scale Quantum (NISQ) computers and forward-looking Fault-Tolerant (FT) quantum computers have fundamentally different constraints such as data locality, instruction parallelism, and communication overhead. Our heuristic-based ancilla-reuse algorithm balances these considerations and fits computations into resource-constrained NISQ or FT quantum machines, throttling parallelism when necessary. To precisely capture the workload of a program, we propose an improved metric, the "active quantum volume," and use this metric to evaluate the effectiveness of our algorithm. Furthermore, our results show that SQUARE improves the average success rate of NISQ applications by 1.47X. Surprisingly, the additional gates for uncomputation create ancilla with better locality, and result in substantially fewer swap gates and less gate noise overall. SQUARE also achieves an average reduction of 1.5X (and up to 9.6X) in active quantum volume for FT machines.

Scalable solutions are essential to achieving the long-term goal of building a fault-tolerant quantum computer and energy-power consumption are fundamental limiting factors for this target. Among the available types of silicon qubits, this work focuses on Flip-Flop (FF) qubits. Energy consumption and power requirements are estimated for a square array of qubits that hosts the logical qubit. The logical qubit is implemented using the rotated Surface Code (SC) for Quantum Error Correction (QEC). By using a universal set of quantum gates, the energy usage, time and power requirements for a SC cycle are estimated based on noise level, code distance and control levels. These estimates are used to provide insights into the main scaling-up challenges for quantum computer development. This is achieved by extending a thermal model that includes energy contributions from both the cryogenic components (such as the qubit array, the cryogenic control electronics, and the cryostat) and the room temperature (RT) section (RT electronics and heat dissipation systems). The maximum numbers of physical and logical qubits are provided, as well as power consumption across the different temperature sections.

We perform logical and physical resource estimation for computing binary elliptic curve discrete logarithms using Shor's algorithm on fault-tolerant quantum computers. We adopt a windowed approach to design our circuit implementation of the algorithm, which comprises repeated applications of elliptic curve point addition operations and table look-ups. Unlike previous work, the point addition operation is implemented exactly, including all exceptional cases. We provide exact logical gate and qubit counts of our algorithm for cryptographically relevant binary field sizes. Furthermore, we estimate the hardware footprint and runtime of our algorithm executed on surface-code matter-based quantum computers with a baseline architecture, where logical qubits have nearest-neighbor connectivity, and on a surface-code photonic fusion-based quantum computer with an active-volume architecture, which enjoys a logarithmic number of non-local connections between logical qubits. At 10% threshold and compared to a baseline device with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1μ s$</tex-math></inline-formula> code cycle, our algorithm runs <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\gtrsim$</tex-math></inline-formula> 2-20 times faster, depending on the operating regime of the hardware and over all considered field sizes, on a photonic active-volume device.

Rapid advancement in the domain of quantum technologies have opened up researchers to the real possibility of experimenting with quantum circuits, and simulating small-scale quantum programs. Nevertheless, the quality of currently available qubits and environmental noise pose a challenge in smooth execution of the quantum circuits. Therefore, efficient design automation flows for mapping a given algorithm to the Noisy Intermediate Scale Quantum (NISQ) computer becomes of utmost importance. State-of-the-art quantum design automation tools are primarily focused on reducing logical depth, gate count and qubit counts with recent emphasis on topology-aware (nearest-neighbour compliance) mapping. In this work, we extend the technology mapping flows to simultaneously consider the topology and gate fidelity constraints while keeping logical depth and gate count as optimization objectives. We provide a comprehensive problem formulation and multi-tier approach towards solving it. The proposed automation flow is compatible with commercial quantum computers, such as IBM QX and Rigetti. Our simulation results over 10 quantum circuit benchmarks, show that the fidelity of the circuit can be improved up to 3.37 × with an average improvement of 1.87 ×.

<p indent="0mm">Recently, the achievement, entitled “lifetime enhancement for a logic qubit by bosonic encoding error correction”, has been selected as one of “The Ten Major Advances in Chinese Science 2023”. Here, we will introduce briefly the importance of this work. It is known that quantum states are fragile due to decoherence induced by environment. Error will happen on a qubit, resulting in continuously changes of the parameters for this qubit, such as amplitude and phase parameters. The aim of quantum error correction is to amend those errors by using various quantum error correction codes, in which a logic qubit can be represented by several physical qubits. It should be noted that the quantum error correction can be realized by correcting a discrete set of errors, such as bit-flip error, phase-flip error or both of them. On the other hand, types of errors occurred depend on specific platforms of quantum computation. For example, photon loss is more inclined to occur in photonic systems. In this case, the approach of bosonic encoding of quantum error correction is more efficient. The work “lifetime enhancement for a logic qubit by bosonic encoding error correction” is for such a scenario. The challenge of quantum error correction is that operation itself is not perfect which may incur new errors. So it is actually difficult to demonstrate that we can benefit from quantum error correction. The achievement of lifetime enhancement by bosonic encoding error correction succeeds in beating this break-even point. The experiments are performed by circuit quantum electrodynamics on a superconducting processor with a qubit and a coupled resonate cavity. The logic qubit is realized by the bosonic mode of the cavity, while the superconducting qubit plays the role of the ancillary qubit in error correction. The initial states are prepared by the superconducting qubit, and are transferred to the logic qubit in the cavity. Then the error correction can be performed based on detection of photon loss by the superconducting qubit. The results show that the lifetime of the logic qubit increases from <sc>694 μs</sc> to <sc>805 μs</sc> with 16% enhancement. Besides high quality devices, the success of this experiment depends on the feedback control to detect and correct the error of photon loss in a short time. The result of beating the break-even point of bosonic encoding error correction is for one logic qubit. In the near future, it is hopeful to implement logic gates, such as single-qubit rotation gate and two-qubit gate, on a couple of logic qubits by bosonic encoding. The importance of the results will depend on whether higher fidelity can be achieved compared with those of gates with physical qubits. In this way, the advantage of the logic qubits for quantum computation is presented. It will be significant that the approach of bosonic encoding with a superconducting processor is scalable to hundreds of logic qubits, which may take a few years to realize. Our aim is to realize a fault-tolerant universal quantum computer based on a large quantity of high-precision logic qubits. The work “lifetime enhancement for a logic qubit by bosonic encoding error correction” is an important step toward this aim.

The variational quantum eigensolver is a promising way to solve the Schrödinger equation on a noisy intermediate-scale quantum (NISQ) computer, while its success relies on a well-designed wave function ansatz. Inspired by the quantum neural network, we propose a new hardware heuristic ansatz where its expressibility can be improved by increasing either the depth or the width of the circuit. Such a character makes this ansatz adaptable to different hardware environments. More importantly, it provides a general framework to improve the efficiency of the quantum resource utilization. For example, on a superconducting quantum computer where circuit depth is usually the bottleneck and the qubits thus cannot be fully used, circuit depth can be significantly reduced by introducing ancilla qubits. Ancilla qubits also make the circuit less sensitive to noises in practical application. These results open a new avenue to develop practical applications of quantum computation in the NISQ era.

While current quantum computers, referred to as Noisy Intermediate-Scale Quantum (NISQ) computers, are expected to be beneficial for different applications, they are prone to different types of errors. In order to enhance the reliability of quantum systems, noise-aware quantum compilers are used to generate physical quantum circuits to be executed on NISQ computers. The quantum hardware is calibrated very frequently and its error rates are computed accordingly. Based on the hardware error rates, a quantum compiler allocates physical qubits and schedules quantum operations. However, error rates may change post-calibration. To incorporate dynamic error rates into quantum circuit compilation with minimum cost, we propose a Machine Learning (ML)-based scheme to detect the incorrect output of the quantum circuit and predict the Probability of Successful Trials (PST) with high accuracy. Our approach can verify the error rates of the quantum hardware and validate the correctness of the extracted quantum circuit output. We provide a case study of our ML-based reliability models using IBM Q16 Melbourne quantum computer. Our results show that the proposed scheme achieves a very high prediction accuracy.

Quantum state preparation is a key step in all digital quantum simulation algorithms. Here we propose methods to initialize on a gate-based quantum computer a general class of quantum spin wave functions, the so-called valence-bond-solid (VBS) states, that are important for two reasons. First, VBS states are the exact ground states of a class of interacting quantum spin models introduced by Affleck, Kennedy, Lieb, and Tasaki (AKLT). Second, the two-dimensional VBS states are universal resource states for measurement-based quantum computing. We find that schemes to prepare VBS states based on their tensor-network representations yield quantum circuits that are too deep to be within reach of noisy intermediate-scale quantum (NISQ) computers. We then apply the general nondeterministic method herein proposed to the preparation of the spin-1 and spin-3/2 VBS states, the ground states of the AKLT models defined in one dimension and in the honeycomb lattice, respectively. Shallow quantum circuits of depth independent of the lattice size are explicitly derived for both cases, making use of optimization schemes that outperform standard basis gate decomposition methods. The probabilistic nature of the proposed routine translates into an average number of repetitions to successfully prepare the VBS state that scales exponentially with the number of lattice sites N. However, two strategies to quadratically reduce this repetition overhead for any bipartite lattice are devised. Our approach should permit to use NISQ processors to explore the AKLT model and variants thereof, outperforming conventional numerical methods in the near future.

Noisy intermediate scale quantum (NISQ) systems are susceptible to errors that culminate in near-one hundred percent data loss. This is due to quantum state fragility and the incredibly high quantum communication error rates caused by decoherence, or quantum noise. As such, stabilizing qubit operational imprecision in quantum information processing is a critical area of research in quantum computing. Adaptive quantum machine learning (QML) methods, like unsupervised and fully entangled quantum generative adversarial networks is one such technology theorized to provide a breakthrough in quantum error suppression. Mechanizing the quantum error detection and correction process with QML provides a path forward from today’s monolithic quantum computers running almost exclusively single-core quantum processing unit (QPU) designs, to the next generation of federated quantum computers using multi-core QPUs. Automating the detection and correction of quantum errors in powerful NISQ devices will pave the way for fault-tolerant quantum computing, making quantum speeds at quantum scale suddenly achievable.

Quantum computing for near-term applications in generative chemistry and drug discovery

We introduce a new method to calculate phase shifts on noisy intermediate scale quantum (NISQ) hardware platforms using a wave packet edge time delay. The method uses the early and intermediate stages of the collision because the standard method based on the asymptotic out-state behavior is unreachable using today’s NISQ platforms. The calculation was implemented on a 4-site transverse Ising model in one spatial dimension with and without a potential interaction. A time evolution operator describing the progression of the system was constructed and transmission and reflection coefficients were calculated based on the identified quantum Fourier transformed momentum states. The detailed analysis of the phase shift calculations on both IBM superconducting transmon and University of Maryland ion trap quantum computers shows the platform independence of the methodology. This successful implementation of this wave packet preparation and projection on momentum eigenstates can now be performed with actual quantum computing hardware platforms. This method provides a procedure for calculating phase shifts and opens the possibility of using noisy intermediate scale quantum devices to perform real-time quantum mechanics and quantum field theory scattering calculations.

Quantum computers are growing at a rapid pace. Trends show that the current decade could be the one in which quantum computers deliver commercial value. Today's quantum computers are overwhelmed by errors. To unlock their massive potential, a significant reduction in errors is required. Several qubit technologies are under research, e.g. superconducting, neutral atoms, trapped ions, photons and silicon. For useful quantum computing on these qubit technologies, Quantum Error Correction (QEC) turns unreliable physical qubits into useful logical qubits. QEC requires solving a real-time, large data volume decoding problem that determines the effect of physical noise on the computation carried out on logical qubits. The nature of the decoding problem depends on the qubit technology, choice of QEC code and mode of quantum computation. These are actively researched subjects in the quantum computing world. Hardware-based decoders that use Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuits (ASIC) technologies are the most promising solutions in terms of speed and scalability. However, the design methodology for these solutions typically suffers from long lead times and a lack of flexibility. We propose GridGenQ, a hardware design utility that automates part of the FPGA/ASIC design methodology for distributed QEC decoders. We show that with our novel solution, development time for such distributed hardware decoders can be reduced from several weeks to few minutes. This allows for fast prototyping of distributed decoder architectures to meet the requirements posed by a dynamic QEC landscape.