Bio-inspired optic flow sensors based on FPGA: Application to Micro-Air-Vehicles

Nature provides us with many examples of ingenious sensors and systems at the service of animal behavior, which can be transferred into innovative systems for the control of MicroAir Vehicles (MAVs). Winged insects demonstrate daunting behaviors in spite of the poor resolution of their visual system. For more than 100 million years, they have been navigating in unfamiliar 3D environments by relying on optic flow (OF) cues. To sense and react to the flowing image of the environment, insects are equipped with smart sensors called Elementary Motion Detectors (EMDs) that can act as optic flow sensors (figure 1). The principle of our bio-inspired optic flow sensors is based on findings obtained at our laboratory on the common housefly’s EMDs, by performing electrophysiological recordings on single neuron while applying optical microstimuli to two single photoreceptors cells within a single ommatidium (Franceschini, 1985, Franceschini et al. 1989). The OF-field gives the angular velocity (in rad/s) at which any contrasting object in the environment is moving past the eye (Koenderink, 1986). One lesson we have learned from insects is that they are able to navigate swiftly through the most unpredictable environments without using any velocimeters or rangefinders. Insects rely on optic flow to avoid collisions (Collett, 1980; Wagner, 1982; Tammero and Dickinson, 2002), to follow a corridor (Kirchner and Srinivasan, 1989; Baird et al. 2005; Ruffier et al., 2007; Serres et al., 2007; Serres et al. 2008), to follow the terrain (William, 1965; Srygley and Oliveira, 2001), to fly against wind (Kennedy 1939, Kennedy 1951), and to cruise and land (Srinivasan et al., 1996), for example. Interestingly, insects seem to maintain a constant optic flow with respect to their surrounding environment while cruising and landing (Kennedy, 1951; David, 1978, Srinivasan et al. 1996, 2000). Several MAV autopilots were built in recent years which show how insects could achieve this feat by using a feedback control system called the optic flow regulator (Ruffier and Franceschini, 2003, 2005, Serres et al. 2008). Future MAVs’ visual guidance systems may have to incorporate optic flow sensors covering various parts of the visual field, like insects do (Figure 2). The biorobotic approach developed at our laboratory over the past 20 years enabled us to construct several terrestrial and aerial robots based on OF sensing (Pichon et al., 1989, Franceschini et al., 1992, 1997; Mura and Franceschini, 1996; Netter and Franceschini., 2002,

This paper presents a digital implementation of 4-D autonomous hyperchaotic system on a Field Programmable Gate Array (FPGA) technology. In the design, the system parameters are selected according to the requirements for obtaining a hyperchaotic behavior. The hyperchaotic nature is theoretically verified by using bifurcation analysis and Lyapunov exponents’ calculus; and experimentally assessed by the FPGA implementation. A master-slave scheme for secure data transmission is used. Active control is applied to carry out the synchronization between the master and the slave. FPGA technology is applied in order to be implemented in digital form the 4-D continuous system using a XILINX VERTEX5 chip. The digital sequence generated from the FPGA device is observed in our experimental setup. The implementation with 32 bits fixed point is chosen; highlighting the role of synchronization mechanisms of chaotic systems in the success of these transmissions.

In this study, an ongoing Project named FPGA Based Digital Electronics Education (FPGA_b_DEEP) is introduced and the advantages of FPGA(Field Programmable Gate Arrays) technology which brought to digital design area are dealt with by using a case study. The Project aims to develop instructive and attractive examples to teach Digital Electronics efficiently and faster. In addition to this, PBL(Project Based Learning) method and Micro Learning method are dealt with at the study separately. PBL method has been used partially at the Project and the studies on Micro Learning for association with the Project are going on recently.

One of the main challenges in Systems designs is the ability to integrate real time high fidelity models on suitable and feasible hardware platforms. Because of its inherited parallelism, FPGA (Field Programmable Gate Arrays) technology achieves sample rates which are typically faster than real time. This can be seen as the last line of defence against the increasing requirements given by high fidelity models. But as most of the FPGA applications are specialised and the FPGA toolsets do not support basic control systems blocks, designs are constructed and optimised manually. This leads to significant effort required in finding feasible hardware FPGA implementations. Therefore, the work in this paper describes how to automatically optimise the most time consuming process found in generic FPGA implementations: the optimisation of the pipelining process. This is constructed on a rigorous mathematical model and achieved using drag and drop floating point HDL (Hardware Description Language) control systems blocks, under System Generator, in Simulink.

Optic flow regulation: the key to aircraft automatic guidance

The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the internal FPGA by implementing scrubbing strategy and thus improve the reliability of the whole system.

Input/output (I/O) port is a group of interfaces that has diverse functional structures of a data processing system use to interconnect with each other. I/O port with handshaking capability is one of the powerful configurations to enable digital communication. The main intention of this project is to design prototype of an input/output port with handshaking capability using Field Programmable Gate Array (FPGA). The main reason of using the FPGA technology is it has unlimited number reprogrammed, cuts developing cost and development time. Xilinx Foundation 2.1i Series software in VHDL description was used as a development tool in this project. The VHDL codes were assimilated into a design and development atmosphere to accomplish many subtasks such as FPGA synthesis, optimization, placement, and routing. The successful design was translated, mapped, routed, and placed onto FPGA Demo Board. XC4010XLPC84 Xilinx FPGA from XC4000XL family was used as a target board. In prototype design, the FPGA pins were connected to a parallel printer port by using a coupled 25-pin DB connector, with a 36-pin Centronics connector cable. The output signals were observed and analyzed by using a logic analyzer.

The new generation of field programmable gate array(FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip(SOPC) developing environment. Therefore, this study presents a speed control integrated circuit(IC) for stepping motor drive under this SOPC environment. The design, using FPGA of Spartan-3E series, has realized a subdivision-variation control system for stepping motor. The bottom-top design method is applied in this study. The scheme integrates the current-feedback SPWM principle, the PI regulating technique, the closed-loop control and EDA design technology. The problem of high-subdivision stepping angle is solved effectively. Experimental results indicate that the control system can improve the control precision of stepping motor and make it run more smoothly.

In this study, Field Programmable Gate Array (FPGA) implementation of Conic Section Function Neural Network (CSFNN) for a classification problem focused on iris plant is presented. This work demonstrates for the first time to our knowledge, the feed-forward computation of CSFNN implementation on FPGA. Using l6-bit floating point arithmetic and the look-up tables (LUTs) for the sigmoid function and the square root function, 83% and 72% of slices and LUTs on Spartan 3-E XC3S1600E are used for the realization of CSFNN with five neurons. The classification results obtained from the FPGA implementation and software simulation show that the accuracy error between two platforms is only 0.1%.

This paper proposes a hardware oriented dropout algorithm for an efficient field-programmable gate array (FPGA) implementation. Dropout is a regularization technique, which is commonly used in neural networks such as multilayer perceptrons (MLPs), convolutional neural networks (CNNs), among others. To generate a dropout mask to randomly drop neurons during training phase, random number generators (RNGs) are usually used in software implementations. However, RNGs consume considerable FPGA resources in hardware implementations. The proposed method is able to minimize the resources required for FPGA implementation of dropout by performing a simple rotation operation to a predefined dropout mask. We apply the proposed method to MLPs and CNNs and evaluate them on MNIST and CIFAR-10 classification. In addition, we employ the proposed method in GoogLeNet training using own dataset to develop a vision system for home service robots. The experimental results demonstrate that the proposed method achieves the same regularized effect as the ordinary dropout algorithm. Logic synthesis results show that the proposed method significantly reduces the consumption of FPGA resources in comparison to the ordinary RNG-based approaches.

As Field programmable Gate Array (FPGA) technology has steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing (DSP) applications. In particular, radar front-end signal processing, an application formerly dominated by custom very large scale integration (VLSI) chips, may now be a prime candidate for migration to FPCA technology. As this paper demonstrates, current FPGA devices have the power and capacity to implement a FIR filter with the performance and specifications of an existing, in-system, front-end signal processing custom VLSI chip. A 512-tap, 18-bit FIR filter was built that could achieve sample rates of 5 MHz (with a clock rate of at least 40 MHz) using Xilinx Virtex FPGA technology, and was demonstrated through simulation. Distributed arithmetic was determined to be the most optimal structure for a FPGA FIR design, although future research may show that fast FIR algorithms or filtering in the frequency domain might give better results.

In this research work, an advanced most modern ACP1000 Nuclear Power Plant is addressed. An enhanced fractional order model of ACP1000 nuclear power plant is adopted with an addition of protection and safety systems. The whole plant model is developed by using innovative hybrid technology of Visual Basic, LabVIEW, Fractional Order and Field Programmable Gate Array (FPGA). A reactor trip system is designed and modeled using FPGA technology in LabVIEW. Plant parameters are systematically modeled and panels are designed in LabVIEW for reactor protection controllers. Twenty one reactor trip controllers are designed and modeled based on complex digital logics using FPGA programming in LabVIEW. Two fractional order trip controllers are designed for over temperature protection and over power protection in LabVIEW. FPGA based safety controllers are designed for Engineered Safety Features (ESF) in LabVIEW. For enhanced model of ACP1000 nuclear power plant, 374 systems are modeled in modular form in Visual Basic Environment. Nine process controllers are configured in ANFIS framework in LabVIEW. In this research work, process controllers are used in conjunction with protection and safety controllers using FPGA. The parametric display of simulations is carried out in Visual Basic. The closed loop performance of proposed protection controllers is evaluated under reactor trip and turbine trip while that of safety controllers are evaluated under inadvertent opening of safety valves of pressurizer. Various parameters are simulated for severe transient conditions and the results are evaluated and validated against reference design data and Final Safety Analysis Report (FSAR) of ACP1000 nuclear power plant. All the results are well within the trip and safety systems design bounds under abnormal and severe operating conditions.

FPGA-based implementation of intelligent predictor for global solar irradiation, Part I: Theory and simulation

This paper presents a thorough discussion of the proposed field-programmable gate array (FPGA) implementation for fringe pattern demodulation using the one-dimensional continuous wavelet transform (1D-CWT) algorithm. This algorithm is also known as wavelet transform profilometry. Initially, the 1D-CWT is programmed using the C programming language and compiled into VHDL using the ImpulseC tool. This VHDL code is implemented on the Altera Cyclone IV GX EP4CGX150DF31C7 FPGA. A fringe pattern image with a size of 512×512 pixels is presented to the FPGA, which processes the image using the 1D-CWT algorithm. The FPGA requires approximately 100 ms to process the image and produce a wrapped phase map. For performance comparison purposes, the 1D-CWT algorithm is programmed using the C language. The C code is then compiled using the Intel compiler version 13.0. The compiled code is run on a Dell Precision state-of-the-art workstation. The time required to process the fringe pattern image is approximately 1 s. In order to further reduce the execution time, the 1D-CWT is reprogramed using Intel Integrated Primitive Performance (IPP) Library Version 7.1. The execution time was reduced to approximately 650 ms. This confirms that at least sixfold speedup was gained using FPGA implementation over a state-of-the-art workstation that executes heavily optimized implementation of the 1D-CWT algorithm.

In this paper we describe a single-node, double precision Field Programmable Gate Array (FPGA) implementation of the Conjugate Gradient algorithm in the context of Lattice Quantum Chromodynamics. As a benchmark of our proposal we invert numerically the Dirac–Wilson operator on a 4-dimensional grid on three Xilinx hardware solutions: Zynq Ultrascale+ evaluation board, the Alveo U250 accelerator and the largest device available on the market, the VU13P device. In our implementation we separate software/hardware parts in such a way that the entire multiplication by the Dirac operator is performed in hardware, and the rest of the algorithm runs on the host. We find out that the FPGA implementation can offer a performance comparable with that obtained using current CPU or Intel’s many core Xeon Phi accelerators. A possible multiple node FPGA-based system is discussed and we argue that power-efficient High Performance Computing (HPC) systems can be implemented using FPGA devices only.