Bridges to Technology: Interfaces, Design Rules, and Libraries

In this paper, a general methodology for design rule development and the CAD tool which implements this methodology, Statistical Design Rule Developer (STRUDEL), are presented. The focus of the proposed approach is the concept of a statistical design rule, which is defined as a geometric design rule with an associated probability of failure. Global lateral variations obtained from FABRICS, and local spot defects obtained from measurements are taken into account when calculating the probability of failure. A failure model which accounts for catastrophic faults has been enhanced to include some parametric faults. STRUDEL can be used as a guide to generate layout design rules and may be extended to a wide range of applications including coarse yield estimation during design rules check.

In this paper, we describe a way to build and explore auxiliary boundary constraints used to layout standard cells. It is required to build an electronic component of VLSI chip, a standard cell, given a set of constraints: geometrical design rules and additional electrical requirements. During layout of standard cells, additional constraints are formulated to avoid possible violations at cell boundaries when cells are abutted in a horizontal row. Current work proposes a flow to compute such auxiliary rules.

An extension to a language-based custom VLSI design approach is proposed in which the designer supplies just enough up-front semantic information to allow a substantial amount of beneficial design consistency checking with a minimum of computation. The computational load is reduced by using a bottom-up hierarchical design approach, with incremental checking as the design is built. The load is also reduced by imposing minor restrictions upon the layout designer, by requiring that all active elements be prechecked, and by attaching type attributes to interconnecting signals. The method is very efficient for highly regular designs. Checks performed are geometrical design rules, connectivity, static electrical consistency, and node rise-and-fall times.

Summary form only given. For many VLSI designs, validation has started to dominate the total design effort. In addition, historical trends are indicating that this problem will continue to grow. For example, data from Intel's lead microprocessor design efforts shows that the number of pre-silicon bugs has increased by a factor of four for every lead project for the last 25 years. If this trend is not broken, Intel's next lead design is likely to have to go through the find the bug, evaluate it, root cause it, it, and validate the fix process tens of thousands of times; potentially overwhelming the validation and design team. Thus one of the most critical goals for improving the design process is to break this bug trend. In the presentation, we introduce the integrated design and verification (IDV) system that has been developed at Intel for the last 5 years. IDV combines the design and validation efforts so that the task of design validation (i.e., Did we capture what we actually wanted?) is significantly simplified by means of a much smaller and much more stable high-level model. Furthermore, when the design is completed, so also is the implementation validation (i.e., Did we implement what we intended?). The latter is accomplished by linking the design process very tightly with the validation process. Although this idea is not new, the combination of correct-by-construction and correct-by-verification and the tight integration of a database of verified results is new and has led to a design environment that allows rapid design in which the validation problem has been significantly reduced. To make the presentation more realistic, we will use the design, from a high-level model to layout, of a floating point execution unit as a driving example. We discuss the early design phase in which the high-level model is refined using algorithmic transformations to a viable micro architecture; continue with the middle level design in which the actual logic implementation is derived and conclude with the final placement and layout stage. Although the design process conceptually is performed sequentially, we will illustrate the tight loop that IDV enables between physical design and logical/micro-architectural design. The latter is a critical component in enabling design convergence. In fact, in today's process technology, integration of physical and logical design is not optional but rather mandatory.

In Chap. 2 we covered technologies and in Chap. 3 we saw how these technologies interface with physical design. Here in Chap. 4 we now provide an end-to-end overview of the physical design process, namely how to physically construct the layout of an electronic circuit. In this chapter we present the fundamental knowledge an engineer must possess to carry out this task. In Chap. 5 we then discuss each of the specific physical design steps in further detail. We begin the chapter by introducing the design flow (Sect. 4.1), design models (Sect. 4.2) and design styles (Sect. 4.3). Next, we investigate various design tasks and related tools (Sect. 4.4), before discussing optimization goals and design constraints (Sect. 4.5). Up to this point our treatise has focused mainly on the digital design flow. In Sect. 4.6 we introduce the characteristics of, and differences between, analog, digital, and mixed-signal design flows. Looking toward the future, we conclude the chapter by presenting two different yet complementary visions for analog-design automation to overcome the analog-digital design gap (Sect. 4.7).

With the resolution enhancement techniques such as OPC (Optical Proximity Correction) and SRAF (Sub-Resolution Assist Features), the size of layout data have grown significantly. It is quite common now to find layout files that are tens of GBs in size. Unlike GDSII which can store data hierarchically, mask data formats such as MEBES are essentially flat and more voluminous. Moreover, polygonal data present in layout data files is fractured, thereby increasing the data volume before getting stored in MEBES data format. This results in huge MEBES files. As per the ITRS roadmap of 2005, for a 45nm half-pitch node that is expected to be in use by 2010, the mask data volume for a single layer is expected to reach up to 825 GB. Storing and transferring such large mask data are issues for which the mask industry needs solutions. Historically, MEBES is the most prevalent EB format in the industry. Moreover, in many Mask Data Preparation (MDP) flows, the MEBES format is being used as the de-facto standard for specifying the fractured EB data even though the final target EB machine might be different. In this paper we present techniques for lossless reversible compression of MEBES data, i.e., when the compressed file is decompressed, the generated uncompressed file matches the original MEBES file bit- by-bit. By applying these compression techniques a compression ratio of 5X to 15X can be obtained. In practice, compressing MEBES files is usually a one-time task, but decompression of compressed files is expected to be done multiple times as every time a compressed MEBES file needs processing, it has to be decompressed. MEBES is essentially an efficient data format and the geometries are stored compactly. As a result the compression/decompression techniques described in this paper are quite computation intensive in order to achieve higher compression ratio. This in turn leads to higher CPU time for compression/decompression compared to generic compressors such as gzip. However, as the format-specific compressors produce higher compression ratios, the disk I/O time for compression and decompression is expected to be less compared to the generic compressors such as gzip and gunzip. In spite of this, the format-specific decompressor is usually 3-5X times slower than the generic decompressor such as gunzip. Since decompression is expected to be done more frequently as compared to compression, speeding up decompression is highly desirable. We present a compression technique for MEBES data which enables multiple process threads to decompress the compressed MEBES data. With the multi-core multiprocessor machines becoming quite inexpensive and common, the multi-threaded decompression is expected to perform close to the disk I/O time on such machines. The paper details out the techniques, experimental results in terms of comparative compression ratios, compression and decompression speed using single threads and multiple threads. The possibility of getting higher compression ratios as well as higher or comparable decompression speed makes it more practical to use format specific reversible compression schemes rather than using generic compressors. Even though, the paper focuses on compression and decompression of MEBES, it can be easily extended to the compression of GDSII [1].

Coupling Of Synthesis And Layout: Challenges And Solutions

Extending classical functional dependencies for physical database design

Wen-Sheng Zhao from Hangzhou University, China, talks to Electronics Letters about the paper ‘Novel electromagnetic bandgap structure for wideband suppression of simultaneous switching noise’, page 1243 Wen-Sheng Zhao My research fields include interconnect modelling, multiphysics simulations and microwave sensor design. My major research topic is signal and power analysis of silicon via (TSV)-based 3D integrated systems. In recent years, the fourth industry revolution has shown an urgent need to develop next generation memory modules. As a key technology of industry 4.0, TSV-based high-bandwidth memory (HBM) has attracted a lot of interest from both the research and industrial worlds. To guarantee the system performance, it is necessary to perform signal/power/thermal integrity analysis for an HBM module. We are currently working on the issues related to the physical design of HBM modules (such as TSV modeling, equaliser design, and power noise suppression). Modern circuits are developing towards miniaturisation, high frequency and low power consumption, which puts strict constraints on the signal and power integrity design. For example, the operating voltages are continuously lowered, thereby limiting noise margin in power distribution network (PDN). Under such circumstances, power/ground noise is becoming a serious problem. To resolve this issue, various techniques including decoupling capacitor and electromagnetic bandgap (EBG) have been proposed and are under study. In comparison with decoupling capacitor, EBG structure can provide wideband noise suppression, and has been widely explored in the chip, package, and board. To improve the system performance, it is always desirable to increase the stopband bandwidth and rejection level of EBG structure. In this Letter, a power plane with coplanar EBG etched in the S-bridge EBG was proposed. With the proposed EBG structure, an ultrawide bandgap from 0.28 to 25 GHz with a high suppression level of -45 dB was achieved. Moreover, the signal integrity performance of the proposed EBG power plane was examined. The signal integrity can be ensured by utilising differential traces as the transmission structure. The proposed design can be used to reduce power/ground noise efficiently for mixed signal systems. We expect the proposed design to provide performance improvements in various mixed-signal systems in the immediate future. Currently, we are also working on developing EBG structures for silicon interposer and on-chip PDN. In the longer term, we expect that the EBG structures can be further explored and used in the physical design optimisation of HBM systems. As the clock frequency of the circuit system is continuously increased, the frequency of the simultaneous switching noise (SSN) also increases. However, the low-frequency components of the noise are not reduced accordingly. Therefore, the major issue we faced was developing a wide stopband EBG structure with a low cutoff frequency. Moreover, as grooves etched on the power/ground plane have an adverse impact on the signal transmission, we had to pay special attention to ensure signal integrity in the EBG design procedure. When we began studying TSV technologies, there was very little real-world deployment. Although several semiconductor giants such as Samsung presented some TSV based memory modules, these systems remained in the laboratory stage. Nowadays, TSV technology has matured, and the TSV-based HBM modules have been used in many graphics processing units since 2015. We are currently working on the physical design and optimisation (including signal and power integrity analysis) for TSV-based integrated systems. We have seen the introduction of many kinds of techniques (e.g., EBG, equaliser, differential signaling, and active decoupling) which will be helpful for future designs. There is no doubt that further improvements are always desirable to promote wide applications of TSV based integrated systems.

Ultra-deep submicron manufacturability impacts physical design (PD) through complex layout rules and large guard-bands for process variability; this creates new requirements for new manufacturing-aware PD technologies. The first part of this tutorial reviews PD complications and methodology changes notably in the detailed routing arena - that arise from subwavelength lithography and deep-submicron manufacturing (antennas, metal planarization and mask-wafer mismatch). Process variations and their sources are taxonomized for modeling and simulation. A framework of design for cost and value is described. The second part covers yield-constrained optimizations in PD, especially corners approaches that escape today's pessimistic or even incorrect corner-based approaches. Statistical timing and noise analyses enable optimization of parametric yield and reliability. Yield-aware cell libraries and analog design rules (as opposed to digital, 0/1 rules) can help designers explore yield-cost tradeoffs, especially for low-volume parts. We then examine performance impact-limited fill insertion which goes beyond mere capacitance rules. Modeling, objectives, and filling strategies are discussed. Finally, we discuss current and near-term prospects for the overall design-to-manufacturing PD methodology. Key aspects include better integrations with analysis and manufacturing interfaces, as well as cost-benefit tradeoffs for regular layout structures that are likely beyond 90 nm, cost optimizations for low-volume production, and the role of robust and/or stochastic optimization in PD.

In this paper, we propose a preliminary design for a fusion-fission hybrid energy reactor (FFHER), based on current fusion science and technology and well-developed fission technology. Design rules are listed and a primary concept blanket with uranium alloy as fuel and water as coolant is put forward. The uranium fuel can be natural uranium, LWR spent fuel, or depleted uranium. The FFHER design can increase the utilization rate of uranium in a comparatively simple way to sustain the development of nuclear energy. The interaction between the fusion neutron and the uranium fuel with the aim of achieving greater energy multiplication and tritium sustainability is studied. Other concept hybrid reactor designs are also reviewed. Integral neutron experiments were carried out to verify the credibility of our proposed physical design. The combination of the physical design with the related thermal hydraulic design, alloy fuel manufacture, and nuclear fuel cycle programs provides the science and technology basis for future development of the FFHER concept in China.

The two stages of database design are logical and physical design. Logical database design, also referred to as , is done first. It is the process of studying the workings of a business organization, constructing a set of tables to store the business data, and understanding the constraints on the data, the dependencies between the tables, and the business rules concerning the data. The logical database design process is conducted without reference to any specific database technology such as Oracle or Microsoft SQL Server. Tools such as SQL Developer Data Modeler and Toad Data Modeler can be used for the purpose. Physical database design follows logical database design. First, the logical model is mapped to the proprietary features of the chosen database technology. Security requirements, integrity requirements, and business rules are also implemented. Finally, you consider performance: the ability of the database engine to handle work requests efficiently. This typically involves the creation of indexes on the data, and Oracle Database provides a wealth of indexing mechanisms to choose from.

Logic design strategies

Placement is a step in the physical design associated with laying the cells of an integrated circuit in a designated area, so that timing, congestion, and utilization goals are met. Placement is a major step in physical design thus, applying optimization methods relies heavily on implementing processes from scratch or the reuse of code that has been previously tested in similar procedures. A modern placer needs to handle large amount of cells with different sizes and placement constraints. For both industry and academia, a toolset comprising widely used functionalities, can be extremely practical and reduce the development and testing cycle. In this paper we present the Bookshelf Format Parser, a management toolset for bookshelf formatted designs, accompanied by an extensive evaluation of its elaborate and versatile architecture. We evaluate the performance of the proposed toolset using benchmarks derived from actual designs. Numerical results depict the performance of the proposed approach in terms of execution time and memory consumption while a comparative assessment reveals the position of the paper in the relevant literature.

The widespread use of computers and the vast development of software have drastically changed the traditional approach of engineering design. Whereas in the past, most of the design work was geared to the proper selection of the system components, today the emphasis is not only focused on the selection of the size and shape of components, but increasingly on the intergration of the individual components into a workable, least-cost system, that generates the greatest gain. This change in approach has been strongly induced by the use of computers and softwares as design tools for automating and improving the quality of the design process. With the introduction of the computer it has become feasible to draft for a given project, at an acceptable cost of production, several alternative designs that fit the local situation, and to select from the feasible solutions the least-cost design. A second main advantage that can be achieved in the design process using computers and software as design tools is the standardization and uniformization of design steps. Although there is not a blueprint for the design process, it can be stated that most agricultural water management design projects involve a large number of similar design steps. By breaking up the design process into a logic hierarchic sequence of design steps, it becomes obvious that similar design modules can be used for the design of a subsurface drainage system as for a micro-jet spray irrigation system. This paper successively highlights the conceptualization of the design process, the similarity between the design steps for agricultural water management projects, a drainage or an irrigation system design, respectively, possibilities of automating the calculation process, and the description of a feasible approach for automating the design process including the drawing of design maps. Throughout the text, a number of examples will be used to illustrate more clearly the impact of the use of computers and software on the design process.