BRISE

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.KeywordsExecution TimeSupply VoltageKnapsack ProblemBasic BlockProgram RegionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Modern real-time embedded systems have increasingly penetrated our daily life and are also often constrained in terms of temperature and energy. In this paper, a thesis is defended that from a real-time systems perspective, thermally constrained dynamic power management approaches behave very similar to idealised dynamic voltage and frequency scaling. Hence, existing dynamic voltage and frequency scaling solutions proposed for periodic/sporadic task models can be applied to thermally constrained dynamic power management systems with moderate effort. This work presents the similarities along with the distinctive elements between two approaches. Within the case study, the porting of a dynamic voltage and frequency scaling algorithm of the literature to thermally constrained dynamic power management system is demonstrated.

Modern information and communication technology along with the broad adaptation of computing paradigms, namely cloud computing has significant impact on environment due to huge amount of CO 2 emission. In the recent decade, a significant growth in the research domain of “green” and low power consumption network has been observed. With the recent advancements of compute intensive machine learning frameworks like deep learning, the energy consumption by GPUs is a challenging issue. In all of these cases, Dynamic Voltage Frequency Scaling (DVFS) has gained significant research interests and shown encouraging outcome. Dynamic Voltage and Frequency Scaling (DVFS) is utilized to reduce the energy consumption in data centers without impacting the Quality of Service. On the other side, spatio-temporal dataset is huge in size and requires compute and time intensive algorithms and techniques for different spatio-temporal query processing. In all aspects, the correlations among energy, DVFS, consolidation, and performance are the key-enablers of energy-efficient management. In this chapter, we explore different existing DVFS techniques and challenges to analyse and process spatio-temporal query in cloud based paradigm. We have considered movement datasets for demonstrating energy consumption and utility of dynamic voltage and frequency scaling.KeywordsDynamic voltage and frequency scalingSpatio-temporal QueryCloud datacenterScheduling algorithmPowerEnergy

Shrinking feature sizes, reduced voltages, and higher transistor count of nano-scale silicon chips challenge designers in terms of performance, power consumption, and reliability. This paper investigates the effect of simultaneous use of dynamic voltage and frequency scaling (DVFS) and body biasing (BB) on power consumption, reliability, and performance. An analytical model of reliability as a function of body bias voltage, supply voltage, and frequency is proposed. We derive a three dimensional optimization problem by exploiting proposed reliability model in conjunction with power consumption and performance model. The resulting problem is solved using widely-used geometric optimization to identify optimal supply voltage and body bias voltage and then is validated using accurate simulation. Afterwards, it is demonstrated how joint energy-performance-reliability space optimization method can be used in an adaptive reliability-aware power management systems. Finally, we show that combined soft error aware BB and DVFS is capable of improving power consumption about 30% in comparison to reliability-aware DVFS only for the same level of reliability and performance constraints.

Chapter 7 - Dynamic Voltage and Frequency Scaling

In designing information communication devices such as real-time embedded systems, it is quite important to maximize the system performance under some hard energy constraints. As a useful technology to reduce the energy consumption in computer-based systems, the dynamic voltage and frequency scaling (DVFS) is becoming very popular. In this paper, we consider an optimal DVFS allocation problem by maximizing the system reliability subject to the hard real-time and energy constraints. More specifically, we formulate a reliability maximization problem when the task processing is probabilistic and is described by a discrete-time Markov chain. Two approximate formulas are proposed to calculate the system reliability efficiently. We perform the sensitivity analysis of model parameters in numerical examples, and also give a case study to design a Wi-Fi subsystem in terms of the DVFS allocation.

Graphics processor (GPU) architectures have evolved rapidly in recent years with increasing performance demanded by 3D graphics applications such as games. However, challenges exist in integrating complex GPUs into mobile devices because of power and energy constraints, motivating the need for energy efficiency in GPUs. While a significant amount of power optimisation research effort has concentrated on the CPU system, GPU power efficiency is a relatively new and important area because the power consumed by GPUs is similar in magnitude to CPU power. Power and energy efficiency can be introduced into GPUs at many different levels: 1) Hardware component level - queue structures, caches, filter arithmetic units, interconnection networks, processor cores, etc., can be optimised for power. 2) Algorithm level - the deep and complex graphics processing computation pipeline can be modified to be energy aware. Shader programs written by the user can be transformed to be energy aware. 3) System level - co-ordination at the level of task allocation, voltage and frequency scaling, etc., requires knowledge and control of several different GPU system components We outline two strategies for applying energy optimisations at different levels of granularity in a GPU: (1) Texture Filter Memory (TFM) - an energy-efficient addition to the texture memory hierarchy component; and (2) an overall system level Dynamic Voltage and Frequency Scaling (DVFS) based energy reduction strategy based on an accurate tile-level slack prediction. Texture Filter Memory is an augmentation of the standard GPU texture cache hierarchy. Instead of a regular data cache hierarchy, we employ a small first level register based structure that is optimised for the relatively predictable memory access stream in the texture filtering computation. Predictability of the memory access patterns leads us to reduce power by using a simpler register access structure. Power is saved by avoiding the expensive tag lookup and comparisons present in regular caches. Further, the texture filter memory is a very small structure, whose access energy is much smaller than a data cache of similar performance. Dynamic Voltage and Frequency Scaling, an established energy management technique, can be applied in GPUs by first predicting the workload in a given frame, and, where sufficient slack exists, lowering the voltage and frequency levels so as to save energy while still completing the work within the frame rendering deadline. We apply DVFS in a tiled graphics renderer, where the workload prediction and voltage/frequency adjustment is performed at a tile-level of granularity, which creates opportunities for on-the-fly correction of prediction inaccuracies, ensuring high frame rates while still delivering low power. Tile-level energy management schemes are distinctly superior to schemes that work at the granularity of the entire frame in terms of energy saving and quality of the rendering measured in terms of frames rendered per second. The prediction mechanism relies both on the history - workload observed for the tile in recent frames, as well as rank - a quantification of the tile workload based on the frame structure, consisting of geometry, pixel shading, texture, and raster operations workloads.

The functionality of embedded systems is ever growing. The computational power of embedded systems is growing to match this demand, with embedded multiprocessor systems becoming more common. The limitations of embedded systems are not always related to chip size but are commonly due to energy and/or power constraints. While it can be possible to embed a more powerful Multiprocessor System on Chip (MPSoC), it is not always possible to provide an energy or power supply that meets its demands within the device’s size and weight requirements. Power management through Dynamic Voltage and Frequency Scaling (DVFS) enables the device to be run at less than its maximum voltage and frequency, allowing high computational capability when necessary while conserving power at other times. Embedded systems commonly perform real-time functionality. A real-time application has an associated formal model to verify that it meets its timing requirements. This formal model is used to perform a worst-case timing analysis to ensure that the application meets its requirements. These models incorporate the worst-case timing of the application’s computation and communication. Timing changes due to power management must also be taken into account, complicating the verification process. The drive for evermore functionality has led to mixed time-criticality systems, in which multiple applications of various timing criticalities share the same (hardware) resources. This complicates the verification process further as the timing interference due to shared resource contention must be taken into account. A monolithic verification effort is therefore traditionally required after system integration and must be carried out again if any modifications are made that affect the timing of any of the applications. The problem that we aim to solve in this work is to enable real-time applications to perform independent execution and power management without violating their timing requirements or invalidating the timing verification of concurrently executing applications. To solve this problem, we contribute the Composable and Predictable Microkernel (CoMik) to composably and predictably virtualise processors. When used in combination with composable and predictable memory controllers and interconnect (as provided by the Composable and Predictable System-on-Chip (CompSOC) platform), these virtual processors cannot interfere with each other’s timing by even a single cycle. If whatever executes on the virtual processors (e.g. an Operating System (OS) or an application directly) has a real-time requirement, it can be verified independently of whatever executes on the concurrent virtual processors and other virtual resources. To enable formally analysable application execution, we contribute the Predictable Operating System (POSe) that enables dataflow applications to be executed on the (virtualised) processor. We contribute a combined application and platform dataflow graph, including an algorithm to automate this process. When annotated with worst-case timings, the combined application and system graph is then used to verify that the application meets its timing requirement. If the application’s performance is better than its requirement (e.g. when the input or platform behaviour are better than worst case), its performance can be reduced using DVFS to achieve a reduction in power consumption. We contribute an off-line convex optimisation that uses the combined application and platform dataflow model to derive static run-time operating frequency levels to achieve low power consumption. The off-line technique is able to exploit static slack in the schedule, but not dynamic run-time slack due to variations in task execution times. Before dynamic slack can be used it must be possible to observe it. For this purpose, CoMik provides independent power, energy and timing accounting per virtual processor. This enables each virtual processor to be assigned individual power and energy budgets and POSe applications to be assigned timing budgets. We contribute a description and model of how energy and power budgets can be distributed between multiple virtual processors, enabling whatever executes on the virtual processor to perform composable independent power-management without affecting the ability of other virtual processors from using their entire budget allocation. Using CoMik’s accounting infrastructure, we also demonstrate how the quality of applications can be dynamically scaled to assist meeting timing, energy or power requirements. We further contribute a distributed dynamic power management policy that enables dataflow applications that are mapped onto multiple (virtual) processors to make distributed dynamic slack observations and local power-management decisions. We demonstrate the applicability of the presented techniques on an implemented Field Programmable Gate Array (FPGA) prototype of a CompSOC hardware platform instance, using an H.263 decoder as a case-study application. We show that our techniques do not only work in theory, but that they are also implementable and implemented.

Although users of high-performance computing are most interested in raw performance, both energy and power consumption have become critical concerns. Some microprocessors allow frequency and voltage scaling, which enables a system to reduce CPU performance and power when the CPU is not on the critical path. When properly directed, such dynamic frequency and voltage scaling can produce significant energy savings with little performance penalty. This paper presents an MPI runtime system that dynamically reduces CPU performance during communication phases in MPI programs. It dynamically identifies such phases and, without profiling or training, selects the CPU frequency in order to minimize energy-delay product. All analysis and subsequent frequency and voltage scaling is within MPI and so is entirely transparent to the application. This means that the large number of existing MPI programs, as well as new ones being developed, can use our system without modification. Results show that the average reduction in energy-delay product over the NAS benchmark suite is 10% - the average energy reduction is 12% while the average execution time increase is only 2.1%

With growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core Dynamic Voltage and Frequency scaling (DVFS) is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real Multiple Input Multiple Output (MIMO) Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved.

The drive towards utilizing green and renewable energy to power large IT data centers is rapidly gaining momentum. Considerable research has gone into developing simulation models to comprehensively study the energy dynamics of different types of data center equipment in order to better understand how best to conserve it. Most of this research has gone towards modeling of servers and switches but relatively less amount of work is available on Storage Area Networks (SAN). Storage Area Networks play a very vital role in the data center architecture by using specialized storage hardware to manage data. In this paper, we have extended the Green Cloud simulator for computing the energy consumed by different SAN components. A simulation environment for SAN has been presented using the 'Dynamic Voltage and Frequency Scaling' (DVFS) and 'Dynamic Shutdown' (DNS) techniques. The simulation results obtained through two SAN prototype models shows the energy consumption of SAN components to vary with the network topology and type of technique used in scheduling of the workloads. Our experimental simulations revealed that there is an increasing percentage of energy savings in DNS mode for both topologies for an increasing number of servers. Results demonstrated up to 35.6% energy savings.

Error detectors/predictors are inevitable for any power and performance constrained designs. Dynamic voltage and frequency scaling can be efficiently implemented using these error detectors/predictors. In this work, we propose a new area and power efficient error predictor for dynamic voltage and frequency scaling application. In the proposed error predictor, the edge of delayed data of master latch is observed in the high phase of the clock to flag a warning signal. The warning signal determines the point of reduction in the supply voltage without any system failure. Compared to pulse-based error predictor, our timing error predictor consumes 17% less power under 100% switching activity and requires 27% less additional area overhead. The functionality of the proposed FF is tested by implementing ISCAS89 benchmark circuits, 16-bit adder, and 16-bit multiplier. A fully automated insertion flow is adopted to implement the block level designs. Using the proposed FF in a block level implementation shows that it can save power up to 33% in the typical corner compared to conventional worst case design.

This paper presents a system level dynamic voltage and frequency scaling (DVFS) technique targeted toward non realtime applications running on a portable embedded system with multiple frequency-adjustable components. The key idea is to balance the frequency of processor core and memory. Some applications may be I/O bound, some may be CPU bound, and the others may be Memory bound. The proposed DVFS technique relies on pre-collected statistical information of different applications to calculate the expected workload for each coming time slice, and then, it adjusts the frequency of processor core, memory, and system bus to meet the timing constraints(with acceptable penalty) and achieves the maximum energy saving. The proposed technique has been tested on the PXA27x (XScale based) [8] embedded platform and the result was exciting, the processor energy saving can achieve up to 70% in memory bound applications, and the timing performance degradation was less than 5%. In CPU bound applications, the energy saving is relatively small, about 20~40%.

The surge in demand for energy-efficient computing has spurred the exploration of cutting-edge techniques to optimize power consumption in modern computing systems. Though the traditional implementation of Dynamic Voltage and Frequency Scaling (DVFS) has proven effective, their traditional implementations lack adaptability, limiting their ability to fully exploit dynamic workload variations. This research presents an innovative solution by integrating proposed Reinforcement Learning (RL) algorithms into DVFS, addressing the limitations of conventional methods. The proposed RL algorithm employs Q-Iearning, a model-free RL technique, to iteratively learn the optimal policy for adjusting CPU voltage and frequency. Our customized algorithm enables autonomous real-time adjustments of voltage and frequency levels, showcasing a remarkable 20% power saving compared to conventional DVFS. The model's adaptability is evident in its capacity to achieve optimal configurations across diverse workloads, emphasizing RL's potential for enhancing energy efficiency in computing systems. As energy efficiency gains paramount importance, this research underscores the pivotal role of RL, in achieving sustainable and optimal performance in computing systems.

Computational power of embedded graphics processing units (GPUs) in mobile system-on-chips has been increasing steadily to provide high quality user experience related to 2D and 3D graphics. Moreover, the architecture of embedded GPUs is evolving from graphic accelerators into streaming multiprocessors, which enables programmers to use GPUs for general parallel processing. Workload variations in mobile GPU applications are explored to discover the potential of dynamic voltage and frequency scaling (DVFS) on embedded GPUs. A DVFS framework which considers GPUs as computing devices, not graphic accelerators, is proposed. The experimental results show that a conventional processor DVFS policy can achieve power reduction of embedded GPUs with reasonable performance degradation.