Buffer sizing in all-optical packet switches

The large growth of telecommunication traffic demand generated by multiple new applications and expected to last at least for the next decade will force telecom operators to consider offering more flexible transport services. All-optical packet switching is a powerful technique to provide this flexibility and to support in a cost-efficient way a wide range of bandwidth consuming applications. After a very brief introduction about the packet-switched network architecture studied in the framework of the ACTS KEOPS project, we describe the structure of the packet-switching node we have defined. We then move into physical and logical analysis of the network including more than 40 network sections based on 160 Gb/s throughput optical packet switching nodes could operate error free. In addition, logical simulations have proved that such networks could provide a quality of service (packet loss rate and packet transfer delay per node) compatible with a large variety of service classes. Both results validate the feasibility of the network concept and pace the way toward a flexible network based on all-optical switching techniques.

All-optical shared-buffer packet switches have been studied intensively in literature and many scheduling algorithms have been proposed. However, these algorithms either suffer from not being able to make resource reservation, or require high time-complexity to compute scheduling assignment for packets. In this paper, we propose a fast scheduling algorithm for all-optical shared-buffer packet switches. In our algorithm, packet scheduling is first formulated as a tree-searching problem. By breaking down the search tree into multiple smaller subsets and assigning each subset to a secondary processor, solutions can be obtained in a much shorter duration since the secondary processors are working in parallel. For instance, a scheduling assignment can be calculated for a packet in 55 ns with 8 processors, and in 25 ns with 64 processors, assuming a processor clock rate of 200 MHz. We show that our algorithm can achieve a loss rate of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> even at load 0.9 for a 32times32 switch.

All-optical packet switching (AOPS) technology is essential to fully utilize the tremendous bandwidth provided by advanced optical communication techniques through forwarding packets in optical domain for the next generation network. However, long packet headers and other complex operations such as table lookup and packet header re-writing still have to be processed electronically for lack of cost-effective optical processing techniques. This not only increases system complexity but also limits packet forwarding speed due to optical-electronic-optical conversion. Lots of work of improving optical processing techniques to realize AOPS is reported in the literature. Differently, this paper proposes a new networking structure to facilitate AOPS realization and support various existing networks through simplifying networking operations. This structure only requires an AOPS node to process a short packet header to forward packets across it with neither table lookup nor header re-writing. Furthermore, it moves high layer addressing issues from packet forwarding mechanisms of routers. Consequently, any changes in addressing schemes such as address space extension do not require changes in the AOPS nodes. It can also support both connection-oriented and connectionless services to carry various types of traffic such as ATM and IP traffic. This structure is mainly based on the hierarchical source routing approach. The analytical results show that average packet header sizes are still acceptable even for long paths consisting of many nodes each of which has a large number of output ports.

An all-optical packet switching using bistable photonic crystal nanocavity memories was demonstrated for the first time. Nanocavity-waveguide coupling systems were configured for 1 × 1, 1 × 2, and 1 × 3 switches for 10-Gb/s optical packet, and they were all operated with an optical bias power of only a few μW. The power is several magnitudes lower than that of previously reported all-optical packet switches incorporating all-optical memories. A theoretical investigation indicated the optimum design for reducing the power consumption even further, and for realizing a higher data-rate capability and higher extinction. A small footprint and integrability are also features of our switches, which make them attractive for constructing an all-optical packet switching subsystem with a view to realizing optical routing on a chip.

We present a 1 × 2 all-optical packet switch. All the processing of the header information is carried out in the optical domain. The optical headers are recognized by employing the two-pulse correlation principle in a semiconductor laser amplifier in loop optical mirror (SLALOM) configuration. The processed header information is stored in an optical flip-flop memory that is based on a symmetric configuration of two coupled lasers. The optical flip-flop memory drives a wavelength routing switch that is based on cross-gain modulation in a semiconductor optical amplifier. We also present an alternative optical packet routing concept that can be used for all-optical buffering of data packets. In this case, an optical threshold function that is based on a asymmetric configuration of two coupled lasers is used to drive a wavelength routing switch. Experimental results are presented for both the 1 × 2 optical packet switch and the optical buffer switch.

All-optical packet switching can overcome limitations of electronic switches in terms of power consumption, speed, cost, and footprint. Switch architectures combining wavelength converters and fiber delay lines provide tunable routing and contention resolution when used with an N×N arrayed waveguide grating (AWG), a key passive optical component to bypass electronic processing limitations. An AWG passively routes either single or multiple input port wavelengths to output ports. A single wavelength per port strategy reduces crosstalk within the AWG, but drastically increases the dimensionality of the device. AWG design constraints due to bandwidth limitations and fabrication processes limit the port number for the foreseeable future to under 100. In order to scale optical switches to emerging network requirements, we must use multiple wavelengths per port. In this paper, we examine several optical router architectures for data center applications using multiple wavelengths per port, and quantify the physical layer impairments. We consider not only the AWG crosstalk, but also Q-factor degradation caused by the multiple wavelength conversions occurring when a packet is buffered for contention resolution. We present the results as a function of the number of recirculations for on–off-keying (OOK) signal formats. While previous work has addressed this issue in terms of accumulated loss, we focus on accumulated intensity noise due to crosstalk and amplified spontaneous emission (ASE). We compare the routing performance of each architecture, and we point out that the AWG crosstalk and accumulated ASE noise during packet recirculation are both critical to the routing performance.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Photonic integration of an all-optical packet switch (AOPS) is a crucial issue since it leads to a great reduction of volume, power consumption, and costs. Recently, a 1<formula formulatype="inline"><tex Notation="TeX">$\, \times \,$</tex></formula>4 AOPS was successfully demonstrated by using an all-optical label extractor/eraser. The label extractor/eraser was implemented by means of fiber Bragg gratings and optical circulators that prevent the photonic integration of the AOPS. Here, we demonstrate a passive and asynchronous photonic integrated all-optical label extractor/eraser by using narrowband silicon–nitride add–drop ring-resonators. By exploiting the narrow bandwidth of the drop port and pass-through port error-free simultaneous separation/erasing of the in-band labels from the 160-Gb/s packet payload was demonstrated without noticeable pulse-shape distortions. </para>

Optical buffering is one major challenge in realizing all-optical packet switching. In this paper we focus on a delay-line buffer architecture, called a Multiple-Input Single-Output FIFO (MISO-FIFO) optical buffer. This architecture reduces the physical size of a buffer by up to an order of magnitude or more by allowing reuse of its basic optical delay line elements. We consider the MISO-FIFO optical buffers in a network scenario where the incoming packets are asynchronous and of variable length. A simple Markov model is developed to analyze the performance of our buffering scheme, in terms of packet loss ratio, average packet delay and the output link utilization. Both simulation and analytical results show that increasing the buffer size will significantly improve the performance of this optical buffer under low system load. However, under high system load, its performance will deteriorate when increasing the buffer size. In addition, this paper gives clear guidelines for designing the optimal basic delay line lengths under different system loads, in order to get the minimal packet loss. It is noticeable that this optimal basic length value is independent of the buffer sizes.

All-optical label swapping (AOLS) forms a key technology towards the implementation of all-optical packet switching nodes (AOPS) for the future optical Internet. The capital expenditures of the deployment of AOLS increases with the size of the label spaces (i.e. the number of used labels), since a special optical device is needed for each recognized label on every node. Label space sizes are affected by the way in which demands are routed. For instance, while shortest-path routing leads to the usage of fewer labels but high link utilization, minimum interference routing leads to the opposite. This paper studies all-optical label stacking (AOLStack), which is an extension of the AOLS architecture. AOLStack aims at reducing label spaces while easing the compromise with link utilization. In this paper, an integer lineal program is proposed with the objective of analyzing the softening of the aforementioned trade-off due to AOLStack. Furthermore, a heuristic aiming at finding good solutions in polynomial-time is proposed as well. Simulation results show that AOLStack either a) reduces the label spaces with a low increase in the link utilization or, similarly, b) uses better the residual bandwidth to decrease the number of labels even more.

Current developments in optical components technologies enable wavelengths to be very narrowly spaced, transforming the optical fiber into a multi-terabit capacity medium. A new generation of cross-connects started to appear in the market leading to a number of advantages such as increased switching capacity, decreased overall network costs, scalability and transparency resulting in the capability to support any protocol. An additional advantage is the ability to configure the switching fabric and the wavelength converters in real-time. All-optical switches are made possible by a number of technologies that allow the managing and switching photonic signals without converting them into electronic signals. Only a couple of technologies appear ready to make the transition form the laboratory to the network, where they must support the basic feature set of a carrier-grade, scalable optical switches. Arguably, the leading technology for developing an economically viable, scalable all-optical , OOO switch is the 3D micro-electromechanical system (MEMS). 3D MEMS uses control mechanisms to tilt mirrors in multiple directions (3 dimensional). For the control of optical cross-connects, the MP Lambdas approach was proposed by IETF, according to which the MPLS traffic engineering control plane is used in optical cross connects. In this paper, evolution of architectures for optical cross-connects all optical switch are discussed with different switch fabrics such as micro-electro-mechanical all optical switch fabric and arrayed-wavelength-grating routers (AWGRs). The paper includes also an illustration of the major function of the multi protocol label switching MPLS optical router and the use of MP lambda switch to control the all optical switch.

In this paper, a new approach for constructing a hierarchical DWDM network is proposed. It is comprised of multiple levels by using a special ring topology. On each network level, one or several ring structures, named as cells here, are employed. The multi-level DWDM network keeps the efficiency of packet-switched network and the simplicity of wavelength-routed network. We perform packet switching at some particular physical nodes on the bottom level. On all upper levels, wavelength routing is performed. As a result, the node configuration and network complexity can be simplified apparently. The performance analysis is provided to verify the feasibility of the proposed approach.

We address the problem of congestion resolution in optical packet switching (OPS). We consider a fairly generic all-optical packet switch architecture with a feedback optical buffer constituted of fiber delay lines (FDL). Two alternatives of switching granularity are addressed for a switch operating in a slotted transfer mode: switching at the slot level (i.e., fixed length packets of a single slot) or at the burst level (variable length packets that are integer multiples of the slot length). For both cases, we show that in spite of the limited queuing resources, acceptable performance in terms of packet loss can be achieved for reasonable hardware resources with an appropriate design of the time/wavelength scheduling algorithms. Depending on the switching units (slots or bursts), an adapted scheduling algorithm needs to be deployed to exploit the bandwidth and buffer resources most efficiently.

The ever increasing intra-chip and inter-chip traffic load in computing systems has been pushing traditional electronic interconnects to their limit in communication bandwidth, latency, and energy consumption. In order to achieve the high bandwidth and low latency required by intra-chip and inter-chip communications and mitigate the high interconnect power dissipation, optical interconnects have been considered as a promising candidate for intra-chip and inter-chip interconnections in next generation computing systems. In addition, packet switching is an efficient switching paradigm to fully utilize the communication bandwidth. However, due to lack of random access optical memory, it is challenging to implement all-optical packet switching in optical interconnects. In this paper, we exploit bufferless routing, a special type of packet-switching, to overcome the problem of lack of random access optical buffer. More specifically, we study bufferless routing in a novel optical multichip system, called Gaussian macrochip, where embedded chips are interconnected by an optical Gaussian network. By taking advantage of the underlying Hamiltonian cycles in the Gaussian network, we design a bufferless routing algorithm for the Gaussian macrochip, which routes packets along the shortest path in the absence of deflection, and guarantees that deflected packets reach their destinations within ${{N}}$ hops. Our extensive simulation results demonstrate that by adopting the proposed routing algorithm, Gaussian macrochip can support much higher inter-chip communication bandwidth, has much shorter average packet delay, and is more power efficient than the previously proposed architectures for optical multichip systems.

We propose an asynchronous optical packet switching node architecture, where congestion resolution is based on shared optical buffers and tuneable wavelength converters. We evaluated our switch by simulations and show that decreasing packet loss probability obtained by optical buffers can be efficiently boosted by adding a few shared tuneable wavelength converters, which allows for reduction of all-optical buffer size. The smaller switch size the larger impact of wavelength conversion on packet loss probability was observed. Furthermore it can be noticed that for the proposed node architecture the higher number of buffer positions the larger improvement caused by applying tuneable wavelength converters can be achieved.

Direct network performance is affected by different design parameters which include number of virtual channels, number of ports, routing algorithm, switching technique, deadlock handling technique, packet size, and buffer size. Another factor that affects network performance is the traffic pattern. In this thesis, we study the effect of hotspot traffic on system performance. Specifically, we study the effect of hotspot factor, hotspot number, and hot spot location on the performance of mesh-based networks. Simulations are run on two network topologies, both the mesh and torus. We pay more attention to meshes because they are widely used in commercial machines. Comparisons between oblivious wormhole switching and chaotic packet switching are reported. Overall packet switching proved to be more efficient in terms of throughput when compared to wormhole switching. In the case of uniform random traffic, it is shown that the differences between chaotic and oblivious routing are indistinguishable. Networks with low number of hotspots show better performance. As the number of hotspots increases network latency tends to increase. It is shown that when the hotspot factor increases, performance of packet switching is better than that of wormhole switching. It is also shown that the location of hotspots affects network performance particularly with the oblivious routers since their achieved latencies proved to be more vulnerable to changes in the hotspot location. It is also shown that the smaller the size of the network the earlier network saturation occurs. Further, it is shown that the chaos router’s adaptivity is useful in this case. Finally, for tori, performance is not greatly affected by hotspot presence. This is mostly due to the symmetric nature of tori.