Bulk-driven feed-forward compensated sub-threshold low-voltage OTA to drive high capacitive load

This paper presents an operational-transconductance-amplifier (OTA) for ultra-low power applications with high CMRR (common mode rejection ratio) and PSRR (power supply rejection ratio). The proposed OTA is a three-stage design. In order to attain the lower supply voltage and high CMRR, a bulk-driven differential pair with the tail current source has been considered as the first stage. The current mirror biasing technique makes sure that all the transistors operate in subthreshold region. A common source amplifier has been opted with current mirror as a load in second stage. At last, common source inverting amplifier is third stage of the designed OTA. The circuit has been designed and synthesized using cadence virtuoso simulator in 180 nm CMOS technology. It has been found that these stages are helpful in achieving high low-frequency gain. Hence, CMRR and PSRR also increase in significant amount. The results describe that the proposed design offers low-frequency gain of 58 dB with CMRR of 72 dB and PSRR of 56 dB for a supply voltage (\( V_{DD} \)) of 0.5 V. The proposed OTA provides the power dissipation of 1.8 µW at \( V_{DD} \) = 0.5 V. Also, the low-frequency gain of 57 dB, CMRR of 70 dB and PSRR of 55 dB with a power dissipation of 2.5 µW have been measured at \( V_{DD} \) = 0.6 V.

This paper presents a novel 0.3V rail-to-rail body-driven three-stage operational transconductance amplifier (OTA). The proposed OTA architecture allows achieving high DC gain in spite of the bulk-driven input. This is due to the doubled body transconductance at the first and third stages, and to a high gain, gate-driven second stage. The bias current in each branch of the OTA is accurately set through gate-driven or bulk-driven current mirrors, thus guaranteeing an outstanding stability of main OTA performance parameters to PVT variations. In the first stage, the input signals drive the bulk terminals of both NMOS and PMOS transistors in a complementary fashion, allowing a rail-to-rail input common mode range (ICMR). The second stage is a gate-driven, complementary pseudo-differential stage with an high DC gain and a local CMFB. The third stage implements the differential-to-single-ended conversion through a body-driven complementary pseudo-differential pair and a gate-driven current mirror. Thanks to the adoption of two fully differential stages with common mode feedback (CMFB) loop, the common-mode rejection ratio (CMRR) in typical conditions is greatly improved with respect to other ultra-low-voltage (ULV) bulk-driven OTAs. The OTA has been fabricated in a commercial 130nm CMOS process from STMicroelectronics. Its area is about 0.002 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mm</i> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and power consumption is less than 35nW at the supply-voltage of 0.3V. With a load capacitance of 35pF, the OTA exhibits a DC gain and a unity-gain frequency of about 85dB and 10kHz, respectively.

This study presents a high common-mode rejection ratio (CMRR), and high power-supply rejection ratio (PSRR) current-mode instrumentation amplifier (CMIA) to overcome the limitations of existing differential voltage second-generation current conveyors (DVCCII)-based CMIAs in achieving high CMRR. The design is based on a fully differential second-generation current conveyor block with a novel circuit design following by a current subtracting stage. The CMIA is designed and laid out in 130 nm CMOS technology operating under ± 1.2 V supply voltage in Cadence software. The post-layout simulation results show that the CMIA achieves low-frequency voltage and current CMRR- BW of 228.8 dB–10 kHz and 246 dB–10.6 kHz, respectively, with PSRR + /PSRR- of 108.2 dB/99.7 dB, power consumption of 507 µW, and a core area of 0.0015 mm2. The unique quality of the circuit is that, it does not need well-matched active blocks, but inherently improves CMRR, bandwidth, and PSRR; hence it gains an excellent choice for integration.

SUMMARY This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18 μm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6 V. The designed IA achieves 30 dB of closedloop gain, 101 dB of common-mode rejection ratio (CMRR) at 50 Hz, 80 dB of power-supply rejection ratio (PSRR) at 50 Hz, thermal noise floor of 53.4 nV/ √ Hz, current consumption of 14 μA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6 V supply from a 0.8–1.0 V energy harvesting power source. It achieves power supply rejection (PSR) of 42 dB at frequency of 1 MHz. A cascode compensated pseudo differential amplifier is used as the filter’s building block for low power design. The filter’s single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6 dB of signalto-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100 Hz sinusoidal maximum input signal, bandwidth of 2 kHz, and power consumption of 51.2 μW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18 μm CMOS process.

In this paper, an instrumentation amplifier (IA) based on operational amplifiers (op-amps) for biomedical applications is presented. Such IA achieves high gain and high common-mode rejection ratio (CMRR) while maintaining low power consumption, high power supply rejection ratio (PSRR) as well as other design constraints. The IA uses three identical two-stage telescopic cascode op-amps at the input and output stages. The feedback networks are comprised of resistors and capacitors, which are different from those in conventional voltage mode IA. The resistive feedback is utilized in the input stage to increase the stability while the capacitive feedback is employed in the output stage to filter undesired frequency components and enhance the gain of the IA. The schematic of IA is designed and simulated under 180 nm CMOS technology using Cadence Spectre tool. The gain and CMRR of the single op-amp are 100.45 dB and 94.8 dB respectively. The power consumed by each op-amp is 12.96 $\mu \mathrm{W}$ at a supply voltage of ± 0.9 V. RC Miller compensation technique helps the op-amp reaching a phase margin of 60°. This IA consumes a power of 38.88 $\mu$W and CMRR of 147.68 dB, with a gain of 101.61 dB. The proposed technique is suitable for a variety of biomedical applications due to its high gain and high CMRR.

A novel operational transconductance amplifier (OTA) having high gain and high bandwidth for high-speed analog communication techniques and precision filtering is designed in this paper. The designed OTA uses β-multiplier-based current biasing scheme with folded cascode amplifier scheme in order to improve the small signal models and the DC gain of circuit. The OTA design was carried out using TSMC 65 nm CMOS technology using Cadence Virtuoso tool with 1 V supply voltage and 10 pf capacitive load. The output DC gain was found to be approximately 75.3 dB. In addition, the unity gain frequency for the designed OTA was found to be around 200 MHz. Superior common mode rejection ratio, power supply rejection ratio and slew rates along with compact chip area and low power are other salient features of the designed OTA. The designed OTA can be employed in order to design high performance analog circuits like data converters, phase-locked loops, etc.

A fifth-order fully-differential CMOS low-pass notch filter (LPNF) with high interference rejection is presented to provide an interface to the instrumentation amplifier (IA) in biopotential and bioimpedance measurement devices. The LPNF employs six operational transconductance amplifiers with differential difference input stage, which have low transconductances in nanosiemens range to enable the use of small capacitors that are feasible for on-chip integration. The filter design was simulated using IBM 0.13-μm CMOS technology. It has a bandwidth of 47.7 Hz, covering the electroencephalography (EEG) frequencies from 1 to 40 Hz with a notch of 73.2 dBc at the 60 Hz power line frequency. The fully-differential structure provides an inherent advantage of high common-mode rejection and high power supply rejection as reflected by system simulations (IA and LPNF) resulting in a common-mode rejection ratio (CMRR) of 101.3 dB and a power supply rejection ratio (PSRR) of 64.7 dB.

This paper presents a high wide band power supply rejection ratio (PSRR) current mode bandgap reference (BGR) with a fast startup performance. The BGR includes three main enhancement techniques to improve the PSRR. The proposed design is implemented in 130nm CMOS technology. It only consumes 50μA from a 1.8V supply. The BGR provides 850mV reference voltage and has a power supply rejection ratio (PSRR) of 130dB from DC to 100Hz and more than 110dB till 100MHz. The temperature coefficient (TC) is 10 ppm/°C from -40°C to 125° C. The Bandgap start-up time is 70ns.

In this paper, a three-stage class AB operational transconductance amplifier (OTA) with large slew rate is presented. The reversed nested Miller compensation technique is used to stabilize the proposed OTA, allowing the slew rate enhancement to be achieved by using class AB input and output stages. A flipped-voltage follower cell in the first stage in combination with a switched-capacitor level shifter in the last stage are utilized to implement the class AB operation. Circuit level simulation results are provided using HSPICE and a 90 nm CMOS technology which show 306 % enhancement in the large-signal FoM with approximately the same power dissipation compared to the class A OTA. The achieved settling time with 0.02 % accuracy for the proposed class AB and conventional class A OTAs are 7.5 and 15.3 ns, respectively.

Power Supply Rejection Ratio (PSRR) is a crucial parameter for Low Drop-out (LDO) linear regulator, which is widely applied in the audio circuit. In order to achieve high PSRR, a high-gain, high-bandwidth error amplifier is necessary. In this paper, we combined lag compensation and miller compensation to implement a high PSRR LDO linear regulator without output capacitors. The LDO structure proposed in this paper was implemented by CSMC 0.5 μm process, simulated by spectre, of which the output reference voltage was 1.8V, and PSRR was 79dB and 70dB at Direct Current(DC) and 20KHz separately, better than 20dB at high frequency.

A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications

A two‐stage Class A‐AB operational transconductance amplifier with low power consumption, high slew rate, and high bandwidth is introduced for handling large capacitive loads. Unlike the conventional two‐stage operational transconductance amplifiers that use a Miller capacitor, compensation is provided by the load capacitor (CL) at the output node. The proposed two‐stage amplifier maintains a 45° phase margin (PM) over any load capacitance. This is achieved through a MOSFET‐based RC network at the output node. Dual nMOS/pMOS differential stages drive output directly, improving both SR+ and SR−. Post‐layout simulation results with a capacitive load of 100 pF (CL) demonstrate that the proposed operational transconductance amplifier has a DC gain of 60.1 dB, an excellent average slew rate of 20.3 V/µs, a gain‐bandwidth product of 10.6 MHz, an average 1% settling time of 122.2 ns and a PM of 76.6°, while consuming only 103.5 µW. Reducing the CL to 10 pF reduces the PM to 47.6°, while increasing the gain‐bandwidth and average slew rate to 82.9 MHz and 142.6 V/µs respectively.

High-performance low dropout regulator (LDO) chips are core components that provide clean power for high-precision sensors, radio frequency (RF) circuits, low noise amplifiers and other noise-sensitive circuits. In the reported literature, the designed LDO chip has advantages in certain parameters, but it cannot meet all the requirements of a high power supply rejection ratio (PSRR), low output noise and low standby current at the same time, which makes the high-end applications of LDOs greatly limited. In this paper, an LDO chip with high PSRR, low output noise and low standby current has been designed and fabricated. By increasing the loop gain, introducing an improved feedforward path, and adopting isolated power supply, the PSRR of the LDO at different frequency bands is greatly improved. By optimizing the design of the error amplifier (EA) and adding a low-pass filter to filter out the reference noise, the output voltage noise of the LDO is reduced. Within the depletion process and an optimized reference structure, the standby power consumption of the LDO is reduced without damaging the output voltage accuracy. The chip is taped out with SMIC’s 0.18 μm/5 V/BCD process. The measured PSRR of the chip is as high as 95dB at a frequency of 1 kHz, and the high-frequency (1 MHz) PSRR is above 45 dB. The amplitude of integrated output noise is below 5.4 μVrms within the frequency range of 10 Hz to 100 KHz. When the load current is zero, the measured standby current is less than 400 nA. The test results indicate that the chip has excellent performance in terms of PSRR, output noise and standby power consumption.

In this paper, a Bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented. On the basis of first-order temperature-compensated BGR, a complementary curvature-compensation technique (CCCT) is realized by using the saturation region current characteristics of PMOS transistors with proportional to absolute temperature (PTAT) bias voltage. Besides, in addition to the effect of cascode structure and the isolation of the current amplifier, the PSRR of proposed BGR is further improved by adopting self-bias power supply with feedback. The presented BGR is implemented in a standard 0.35 μm BCD process. The post-simulation results show that the TC of the BGR is 4.740 ppm/∘C with a 2.50V average output voltage, and the PSRR is up to -78.5dB.

A low power consumer capacitor-less low dropout regulator (LDO) with supper class AB CMOS operational transconductance amplifier (OTA) has been proposed in this paper. The OTA of this design is based on the combination of class AB differential input stages and local common-mode feedback which provides additional common-mode sensing techniques thus to obtain a high common mode rejection ratio (CMRR). Local common-mode feedback (LCMFB) is applied to various class AB differential input stages, leading to different class AB OTA topologies. The presented LDO is fabricated in a 0.18 um standard CMOS process. The circuit consumes a quiescent current of 1.37 uA, regulating the output at 1.0 V with maximum output current of 600 mA from a voltage supply of 1.2V. It achieved full range stability from 1mA to 100 mA load current at a maximum 100pf load capacitor.