Cache memory replacement policy for a uniprocessor system

This article describes how the named data networking (NDN) has recently received a lot of attention as a potential information-centric networking (ICN) architecture for the future Internet. The NDN paradigm has a great potential to efficiently address and solve the current seminal IP-based IoT architecture issues and requirements. NDN can be used with different sets of caching algorithms and caching replacement policies. The authors investigate the most suitable combination of these two features to be implemented in an IoT environment. For this purpose, the authors first reviewed the current research and development progress in ICN, then they conduct a qualitative comparative study of the relevant ICN proposals and discuss the suitability of the NDN as a promising architecture for IoT. Finally, they evaluate the performance of NDN in an IoT environment with different caching algorithms and replacement policies. The obtained results show that the consumer-cache caching algorithm used with the Random Replacement (RR) policy significantly improve NDN content validity in an IoT environment.

Two performance gaps in the memory hierarchy, between CPU cache and main memory, and main memory and mass storage, will become increasingly severe bottlenecks for computing-system performance. Although it is necessary to increase memory capacity to fill these gaps, power also increases when conventional volatile memories are used. A new nonvolatile memory for this purpose has been anticipated. Storage class memory is used to fill the second gap. Many candidates exist: ReRAM, PRAM, and 3D-cross point type with resistive change RAM. However, nonvolatile last level cache (LLC) is used to fill the first gap. Advanced STT-MRAM has achieved sub-4ns read and write accesses with perpendicular magnetic tunnel junctions (p-MTJ) [1–2]. Furthermore, mature integration processes have been developed and 8Mb STT-MRAM with sub-5ns operation has shown high reliability [3]. Moreover, because of its non-volatility, STT-MRAM can reduce operation energy by more than 81% compared to SRAM for cache [1]. This paper presents STT-MRAM-based last level cache memory (LLC) including MRAM memory core, peripherals and cache logic circuits, using novel power optimization with high-speed power gating (HS-PG),considering processor architectures and cache memory accesses. The STT-MRAM-based cache has high reliability to reduce the write-error rate with novel write-verify-write. Furthermore, a read-modify-write scheme is implemented to reduce active power without penalty. Figure 7.2.1 presents a block diagram of a 4Mb STT-MRAM based cache.

Summary form only given. An approach towards an information theoretic based analysis and design of cache memories is presented. Computer systems usually have a slow main memory and a faster cache memory, usually much smaller than the main memory because of its cost. A somewhat similar situation is present also in Internet servers. A miss happens whenever an item is not found in the cache memory. If so, the item is fetched from the main memory and placed in the cache. A hit is obtained whenever the item is found in the cache. Usually the cost of a miss is several times that of a hit. The goal is to find strategies for the many to one mapping of addresses of the main memory to the cache memory, as well as the replacement strategies. Usual replacement strategies are least recently used, LRU, random replacement, RR, etc. The main goal is to obtain strategies that will optimize the running time of the program under execution. Since almost all programs use branch instructions and loops, some of the information theoretic approaches previously introduced consider the prediction of the result of a branch based on its past behavior. Here a different approach is considered. In particular the opposite case is analysed, i.e. a linear loop that is executed indefinitely. In particular a combined random replacement and least recently used strategy is analyzed. It is shown that this model is equivalent to the one of classifying N objects in M classes with at least c objects in each class, and that this problem gives a generalization of the Ehrenfests' urn model used in statistical thermodynamics in connection with the Boltzmann H-theorem.

We consider the problem of on-chip L2 cache management and replacement policies. We propose a new adaptive cache replacement policy, called Dueling CLOCK (DC), that has several advantages over the Least Recently Used (LRU) cache replacement policy.

Due to the ever increasing performance gap between the processor and the main memory, it becomes crucial to bridge that gap by designing an efficient memory hierarchy capable of reducing the average memory access time. The cache replacement algorithm plays a central role in designing an efficient memory hierarchy. Many of the recent studies in cache replacement algorithms have focused on improving L2 cache replacement algorithms by minimizing the miss count. However, depending on the dependency chain, cache miss bursts, and other factors, a processor's ability to partially hide the cost of an L2 cache miss varies; that is, cache miss costs are not uniform. Therefore, a better solution would account also for the aggregate miss cost in designing cache replacement algorithms. Our proposed solution combines the two principles of locality and cost-sensitivity into one which we call: LACS: Locality-Aware Cost-Sensitive cache replacement algorithm. LACS estimates a cache block's cost from the number of instructions the processor manages to issue during a cache miss on that block and then victimizes cache blocks with low cost and poor locality in order to maximize the overall cache performance. When LACS is evaluated using a uniprocessor architecture model, it speeds up 10 L2 cache performance-constrained SPEC CPU2000 benchmarks by up to 85% and 15% on average while not slowing down any of the 20 SPEC CPU2000 benchmarks evaluated. When evaluated using a dual-core CMP architecture model, LACS speeds up 6 SPEC CPU2000 benchmark pairs by up to 44% and 11% on average.

To estimate the prevalence and frequency of amphetamine use in a cohort of Australians aged in their mid-30s. Cross-sectional analysis of wave 10 data collected in 2014 from the Victorian Adolescent Health Cohort Study: a sample of 1435 persons originally selected in a stratified, random community survey of secondary school students from the state of Victoria that commenced in 1992. Weighted multinomial regression models were used to evaluate the social, health and other substance-use correlates of lifetime and current (12-month) amphetamine use and current frequency of use. Lifetime amphetamine use was reported by 23.2% (95% confidence interval 21.0-25.5%) of respondents, and 6.5% (95% confidence interval 5.2-7.8%) reported current (12-month) use. A quarter (26%) of those currently using amphetamines, 1.7% (95% confidence interval 1.0-2.4%) of all respondents, reported frequent (at least weekly) use. Men reported greater amphetamine use than women. Current amphetamine use was associated with disrupted family circumstances, socioeconomic adversity, polydrug use and high levels of drug use within the social and familial environment. Frequent use was associated with greater likelihood of multiple adversity, unemployment, anxiety disorders and use of mental health services. The current results show that lifetime, current and frequent amphetamine use was common amongst adults in the fourth decade of life in this cohort, and associated with the experience of social disadvantage, poor mental health and living in a social context in which drug use is the norm.

Reliability improvement in private non-uniform cache architecture using two enhanced structures for coherence protocols and replacement policies

Due to the increasing gap between CPU and memory speed, cache performance plays an increasingly critical role in determining the overall performance of microprocessor systems. One of the important factors that a affect cache performance is the cache replacement policy. Despite the importance, current analytical cache performance models ignore the impact of cache replacement policies on cache performance. To the best of our knowledge, this paper is the first to propose an analytical model which predicts the performance of cache replacement policies. The input to our model is a simple circular sequence profiling of each application, which requires very little storage overhead. The output of the model is the predicted miss rates of an application under different replacement policies. The model is based on probability theory and utilizes Markov processes to compute each cache access' miss probability. The model realistic assumptions and relies solely on the statistical properties of the application, without relying on heuristics or rules of thumbs. The model's run time is less than 0.1 seconds, much lower than that of trace simulations. We validate the model by comparing the predicted miss rates of seventeen Spec2000 and NAS benchmark applications against miss rates obtained by detailed execution-driven simulations, across a range of different cache sizes, associativities, and four replacement policies, and show that the model is very accurate. The model's average prediction error is 1.41%,and there are only 14 out of 952 validation points in which the prediction errors are larger than 10%.

By rapid growth of the Internet users and devices, thenumber of servers also increase simultaneously which causes the exponentialincrement of the internet traffic and static data. Handling these huge amountsof user requests and efficiently responding to them require high bandwidthlinks, powerful servers and robust equipment, which despite the availability ofthese requirements getting the full user satisfaction is extremely difficultand a tough challenge. In order to overcome the mentioned problem, the cacheservers are being used as a suitable solution. The performance of web cacheserver directly depends on its replacement policies. Several cache replacementpolicies have been proposed in literature each having varied hit rate (HR) andbyte hit rate (BHR) performances on different networks. The replacement policyproposed in this paper is a dynamic cache replacement policy which trainsitself utilizing previous network logs and by exploiting the data miningclustering algorithm. Once the training step is completed, the proposed policyutilizes the normalization formulas to score each metric of the enquiriesincluding recency, frequency, size and delay. Simulation results showed thatthe proposed policy has the optimum performance on different networks and itnot only improved the performance of web cache server in term of HR and BHR,but also decreases the data retrieval time (Delay Ratio (DR)) of the cacheservers.

The performance of computing systems has been improved significantly for several decades. However, increasing the throughput of recent CPUs (Central Processing Units) is restricted by power consumption and thermal issues. GPUs (Graphics Processing Units) are recognized as efficient computing platform with powerful hardware resources to support CPUs in computing systems. Unlike CPUs, there is a large number of CUDA (Compute Unified Device Architecture) cores in GPUs, hence, some cache blocks are referenced many times repeatedly. If those cache blocks reside in the cache for long time, hit rates can be improved. On the other hand, many cache blocks are referenced only once and never referenced again in the cache. These blocks waste cache memory space, resulting in reduced GPU performance. Conventional LRU replacement policy cannot consider the problems from non-reused cache blocks and frequently-reused cache blocks. In this paper, a new cache replacement policy based on the reuse pattern of cache blocks is proposed. The proposed cache replacement policy manages cache blocks by separating reused cache blocks and thrashing cache blocks. According to simulation results, the proposed cache reuse replacement policy can increase IPC by up to 4.4% compared to the conventional GPU architecture.

Random Access Memory plays a crucial role in data processing in various computing systems for faster applications. A processor always fetches the data from the main memory for processing, sometimes the same data may be required for the processing and need to be fetched repeatedly from the main memory results time consuming. Cache memory supports faster data storage and access by storing instances of programs and data which is routinely accessed by the processor. Therefore, the cache memory is used to store recently fetched data and when a processor requests to fetch the data the controller will first check the data in cache, if the fetched data is there in the cache then it will be fetched otherwise the controller will fetch the data from the main memory. Therefore, the cache memory is useful for improving speed of processing without wasting much time for fetching the repeated data. This paper deals with various structures of single ended S-RAM cells and proposes a novel three transistor S -RAM cell design Using Tanner 45nm Technology.

Data caching in mobile clients is an important technique to enhance data availability and to improve data access time. Due to cache size limitations, cache replacement policies are used to find a suitable subset of items for eviction from the cache. In this paper, we study the issues of cache replacement for location-dependent data under a geometric location model and we have proposed a new cache replacement policy RAAR (Re-entry probability, Area of valid scope, Age, Rate of Access) by taking into account the spatial and temporal parameters. The experimental evaluations using synthetic datasets show that our replacement policy is effective in improving the system performance in terms of the cache hit ratio of mobile clients.

In previous research on cache replacement policies, have seen that a block usually becomes dead after some uses. By classifying the dead block and discarding them early, there are various policies have been used but still there are number of problems such as cache pollution, high cache miss rate and cache overhead existed which degrades the system performance. In this paper, a new approach for cache replacement policy has introduced which reduces the cache miss rate and cache overhead by using shared L2 level cache. In terms of less miss rate and good hit rate there is need to deploy effective replacement policies. Cache replacement techniques is one of the crucial design parameter that affects the overall processor performance and also become more important with current growing technological moves in the direction of high associative cache . Keywords: Cache pollution; Cache overhead; Cache miss rate; Cache replacement policy (LRU and LFU); Memory overhead;

Cache memories in modern embedded processors are known to improve average memory access performance. Unfortunately, they are also known to represent a major source of unpredictability for hard real-time workload. One of the main limitations of typical caches is that content selection and replacement is entirely performed in hardware. As such, it is hard to control the cache behavior in software to favor caching of blocks that are known to have an impact on an application's worst-case execution time (WCET). In this paper, we consider a cache replacement policy, namely DM-LRU, that allows system designers to prioritize caching of memory blocks that are known to have an important impact on an application's WCET. Considering a single-core, single-level cache hierarchy, we describe an abstract interpretation-based timing analysis for DM-LRU. We implement the proposed analysis in a self-contained toolkit and study its qualitative properties on a set of representative benchmarks. Apart from being useful to compute the WCET when DM-LRU or similar policies are used, the proposed analysis can allow designers to perform WCET impact-aware selection of content to be retained in cache.

This work shows how by adapting replacement policies in contemporary cache hierarchies it is possible to extend the lifespan of a write endurance-limited main memory by almost one order of magnitude. The inception of this idea is that during cache residency 1) blocks are modified in a bimodal way: either most of the content of the block is modified or most of the content of the block never changes, and 2) in most applications, the majority of blocks are only slightly modified. When those facts are considered by the cache replacement algorithms, it is possible to significantly reduce the number of bit-flips per write-back to main memory. Our proposal favors the off-chip eviction of slightly modified blocks according to an adaptive replacement algorithm that operates coordinately in L2 and L3. This way it is possible to improve significantly system memory lifetime, with negligible performance degradation. We found that using a few bits per block to track changes in cache blocks with respect to the main memory content is enough. With a slightly modified sectored LRU and a simple cache performance predictor it is possible to achieve a simple implementation with minimal cost in area and no impact on cache access time. On average, our proposal increases the memory lifetime obtained with an LRU policy up to 10 times (10×) and 15 times (15×) when combined with other memory centric techniques. In both cases, the performance degradation could be considered negligible.