Calculation Model and Optimization of Epitaxial Layer Thickness based on Multi-beam Interference Using Nonlinear Least Squares Method

The state-of-the-art power switching devices made from SiC and GaN semiconductors contain a high density of crystal defects. Most of these defects are present in starting wafers and some are generated during device processing. There is little conclusive evidence so far on the exact role that the crystal defects play on device performance, manufacturing yield, and more importantly, long-term field-reliability especially when devices are operating under extreme stressful environments. This paper provides a review of the current state-of-the-art of SiC and GaN power semiconductor material technology, and the potential impact crystal defects may have on high-density power switching electronics. Group III-Nitride materials suffer from both extended and point defects, each of which will challenge the material’s application in both vertical and lateral power devices. The extended defects include vertical threading dislocations of both edge and screw type. The latter defects have been shown to be correlated to leakage in vertical two terminal device structures while the influence of the former is still undetermined and remains a critical research issue. Channel surfaces in vertical three terminal devices will also degrade due to vertical threading dislocations. These extended defects occur in all epitaxial layers grown on c-plane substrates (the predominant and largest area substrate type) and are the result of the lack of a high quality substrate bulk material as well as substrate surface. The present substrate technology after multiple efforts (either GaN, SiC or Si) still have a high defect density indicating that low-defect seeds may be non-existing. Point defects influence the background carrier concentration in low-doped layers and various recombination processes. The intrinsic nature of III-N materials makes nitrogen-vacancies a predominant point defect that automatically dopes the crystal n-type, but there are impurities (oxygen and carbon) from most growth environments that also contribute to conductivity. These defects are not well understood and not well controlled. Such defects must be minimized in order to realize thick epitaxial layers with drift regions that will support both high blocking voltages and low on-state resistances. A wide range of materials characterization methods have been applied to further understand these impurities. The semiconductor and dielectric materials used in the construction of power electronics switching devices employed for energy efficiency applications experience extreme electrical and thermal stresses during the on-state as well as when switching high voltages and high currents. For example, in a bipolar type power semiconductor switching device in order to achieve significant conductivity modulation and reduce the drift-region resistance, high-level injection of minority carriers is typical. If the semiconductor contains a high density of crystal defects, as is the case with WBG semiconductors, minority carrier recombination phenomenon can be adversely affected. For example, it has been shown more than a decade ago [3, 4] that basal plane dislocations (BPDs) present in SiC are excited by the energy released from minority carrier recombination process; the result is excess BPD generation and its glide within the semiconductor material that leads to an increase in the drift-region resistance and thermal run-away in a forward biased bipolar junction diode The reported experimental data for high-voltage SiC semiconductor strongly suggests that material defects have profound impact on its characteristics under extreme environments. Since GaN semiconductor has even higher density of material defects, this problem is further exacerbated especially in thick epitaxial GaN layers which are required for power switches beyond 5kV. The integration of the pillar junction scheme with the trench-gate GaN MOSFET processes developed at the University of Maryland will be reported. The thick pillar junction epitaxial layers have been grown by a commercial vendor, using a windowed GaN growth process and/or selective deep etching, followed by GaN regrowth to fabricate columns with opposite carrier polarities. The doping density of the n--pillars under the gate has been specified with background carrier concentration n ≤ 1x1016 cm-3, while the p-pillars will have a higher doping density (p ≥ 1x1018 cm-3) to maximize depletion in the n--pillar. The p-body and n+-source layers are grown by subsequent epitaxial growth across the whole structure. Our current research into optimized trench gate fabrication and gate dielectric processing has been used to fabricate gate trenches into the structure. These devices can be compared to traditional trench MOSFETs with extremely thick blocking layers of comparable thickness to the pillar junction layer in order to determine the role of defects in thick GaN epi layers in terms of limiting device performance and reliability.

Silicon carbide is the core semiconductor electronic material, and the thickness of its epitaxial layer is the key parameter to determine the performance of semiconductor devices, and infrared interferometry is the mainstream thickness measurement technology. Based on the principle of multi-beam interference, combined with Snell's law and Fresnel formula to construct the model, the envelope normalization method is proposed to eliminate the multi-beam modulation interference; Adjacent extreme value method, multi-point linear regression method and full spectrum nonlinear least squares fitting method were designed to fit different SNR data, and Fourier transform infrared spectrometer was used to obtain 10 ° and 15 ° incident angle spectral data for verification. The results show that the relative error of the multi-beam model thickness inversion is only 0. 13%, the residual error of the full spectrum fitting method is randomly distributed with zero mean, and the results of different incident angles are consistent. This study improves the accuracy and robustness of thickness measurement, provides theoretical and methodological support for the detection standard of silicon carbide epitaxial layer, and promotes the high-quality development of semiconductor industry.

The thickness of silicon carbide (SiC) epitaxial layers plays a pivotal role in determining the performance of power devices. Infrared interferometry, as a rapid and non-destructive measurement technique, is often influenced in practice by the multi-beam interference effect occurring at the epitaxial layer–substrate interface—a phenomenon frequently overlooked in conventional models. This study aims to quantitatively evaluate the impact of multi-beam interference and establish a high-precision correction model for thickness measurement. By integrating the Sellmeier equation and the Drude model, we accurately characterize the refractive index dispersion and carrier concentration effects in doped SiC epitaxial layers. A forward model of multi-beam interference based on the transfer matrix method (TMM) is developed to simulate infrared light propagation in multilayer structures. An inversion algorithm combining nonlinear least squares fitting and Monte Carlo simulation is employed to extract the epitaxial layer thickness from experimental reflection spectra. Our results reveal that multi-beam interference introduces a systematic positive bias of approximately 13%. After correction, the measured thickness is adjusted from about 5.5 μm to approximately 6.21 μm. Sensitivity analysis and robustness tests confirm that the results are insensitive to fluctuations in key parameters and exhibit high reliability. This work provides a versatile theoretical model and a practical correction scheme for addressing systematic errors in infrared interferometric thickness measurement of semiconductor films, offering valuable insights for enhancing semiconductor process quality control.

As a simple and non-destructive analytical technique, infrared interference spectroscopy is of great value in improving device manufacturing performance due to its ability to accurately measure epitaxial layer thickness. Based on a single-reflection and transmission model, this paper establishes theoretical models for calculating epitaxial layer thickness under two scenarios depending on whether the substrate refractive index is greater or smaller than that of the vacuum. By utilizing the property that substrates with higher carrier concentrations exhibit larger refractive indices, and combining the optical path differences between adjacent beams, an overall interference expression is derived from interference principles. This yields the relationship between fringe order and wavelength, leading to an algorithmic formula for epitaxial layer thickness. Meanwhile, variations in reflectivity are treated as shifts in interference peaks during experiments; adjacent peak values are extracted, corresponding wavenumbers and interference fringe orders are identified, and the thickness is calculated under a given angle of incidence. Under these conditions, two methods are employed to determine the refractive index of the epitaxial layer. In summary, this study provides a theoretical analysis of epitaxial layer thickness and verifies its accuracy through reliability assessments. The proposed methodological framework holds potential for broader application.

In semiconductor manufacturing processes, silicon dioxide films are commonly used as barrier layers, insulating layers, and protective layers. Coherence scanning interferometry (CSI) offers thin-film thickness measurements with a millimeter-scale field of view and micrometer-scale lateral resolution. When the film thickness is less than the coherence length of a CSI system, a model-based film thickness measurement method is typically employed, which relies on a priori information about the thin film and the instrument. This study quantitatively analyzes how the accuracy of a priori information would affect the accuracy of thickness measurement when using a model-based CSI method. The influence factors include camera noise, numerical aperture (NA), pupil apodization, light source spectrum, and thin-film refractive index. A series of SiO2/Si thin films with varying thicknesses is analyzed by combining simulation and experimental approaches. The results reveal that the accuracy of thickness measurements exhibits varying sensitivity to different a priori information. The refractive index of the thin film is identified as the most sensitive source of error, where a 1% deviation in the refractive index may cause a 1% relative thickness error, whereas a 5% deviation in the NA results in less than a 1% relative thickness error. The simulation and experimental results show good agreement.

The thickness of InGaAsP (λg=1.15 μm) and InGaAs (λg=1.68 μm) liquid phase epitaxial layers grown on (100) InP substrates by the step-cooling technique has been measured as a function of growth time. (λg is defined as the wavelength corresponding to the energy gap of the epitaxial layer.) For growth times much less than the shortest diffusion time τi=l2/Di of the melt constituents, where l is the melt height and Di is the diffusivity of each component in the melt, the thickness is consistent with diffusion-limited theory, and the composition is constant. The time at which the growth rate deviates sharply from diffusion-limited theory and beyond which constant composition growth can no longer be maintained has been determined for the melt size used in our experiments and can be estimated for any melt size.

The domain structure of ferroelectric or ferroelastic materials, arising as a result of the cubic-tetragonal transition inside an epitaxial layer, are considered. A thermodynamic theory of the size and arrangement of the domains has been developed. The dependence of the equilibrium domain structure on the epitaxial layer thickness has been shown.

Strain in thick epitaxial layers

Because the rate of indirect photon-electron conversion for scintillator materials coupled with arrays of photodiodes is at least 25 times smaller than the rate of direct conversion, we examine the conditions to be fulfilled by semiconductors undergoing such direct conversion to be applied to x-ray imaging. Bulk grown materials are not well suited to this application, because large defect concentrations give rise to strongly nonuniform electronic properties. We argue that only epitaxial layers are suitable for use as imaging devices and we illustrate our argument using the case of thick epitaxial GaAs layers. Detectors made with such layers exhibit a good energy resolution, a charge collection efficiency which approaches 1, linearity over more than three orders of amplitude, no afterglow (a response time shorter than 20 μs), and no charge-induced polarization effects.

Silicon carbide is an attractive material for next-generation power devices, it has wide band gap and high thermal conductivity. SiC power devices can operate at higher temperatures and voltages compared to silicon devices. But, electrical characteristics of the SiC power devices can be deteriorated by SiC defects. The killer defects such as micropipes and stacking faults have been reduced through the development of SiC growth technique. But still the threading dislocations (TDs) and basal plane dislocations (BPDs) lowered the breakdown voltage and increased the leakage current during device operation [1]. In this study, we fabricated the 5 kV 4H-SiC Schottky barrier diode (SBD) to study the effect of SiC defect on electrical properties of SiC SBDs. The thickness of epitaxial layer was 50 um and the doping concentration is 1E15 cm-3. The device was fabricated with various length of junction termination extension (JTE). Ion implantation was performed to form p surge (Al, 500 °C, 5E19 cm-3) and JTE (B, 500 °C, 2E18 cm-3) regions. Activation annealing was performed at 1700 °C for 60 m. 100 and 30-nm-thick Ni were deposited as the cathode and front-side ohmic metal respectively, and then annealed at 950 °C for 90 s in RTA system. Finally, 100-nm-thick Ni was sputtered on front-side as a Schottky contact metal. We investigated the forward, reverse characteristics, and reverse breakdown voltage of the fabricated 4H-SiC SBDs. The diode characteristics, ideality factor (IF) and Schottky barrier height (SBH) were obtained from the forward electrical characteristics, about the 1.23 and 1.3 eV, respectively. The relative highly ideality factor may be due to rough surface of thick epitaxial layer. The breakdown voltage was obtained above 5 kV with JTE length longer than 60 um. During reverse characteristics the electrically weak points were observed using electroluminescence (EL). The EL spot was mainly aroused from electrically leaky points, it mostly observed at the edge of JTE. Some EL spots were observed inside the JTE or active region. The defects of the fabricated 4H-SiC 5 kV SBDs were analyzed using non-destructive analysis method, X-ray topography (XRT) and electron beam induced current (EBIC). We tried to determine the correlation between the electrical characteristics of the device and the crystal defects in the device. [1] H. Fujiwara, H. Naruoka, M. Konishi, K. Hamada, T. Katsuno, T. Ishikawa, Y. Watanabe, and T. Endo, Appl. Phys. Lett. 100, 242102 (2012). Figure 1

An improved method for measuring epi-wafer thickness based on the infrared interference principle: Addressing interference quality and multiple interferences in double-layer structures

We have, for the first time, demonstrated silicon MOSFET's with an ultra-thin epitaxial channel grown by low-temperature UHV-CVD; this allows the channel region to be doped with high precision. The boron concentration and epitaxial layer thickness can be chosen independently, so it is easily possible to adjust the threshold voltage of the p-MOSFET's even in the case of n-type polysilicon gates. It was confirmed that choosing an ultra-thin epitaxial layer-in the 10 nm range-leads to suppression of the short-channel effects in n-type polysilicon gate buried-channel MOSFET's, while maintaining an appropriate value of threshold voltage. >

Displacement damage effects in backside illuminated CMOS image sensors (BSI CISs) are investigated. Several BSI CISs with distinct epitaxial layer thicknesses are irradiated by several protons and neutrons to study the influence of technology parameters and radiation parameters on the radiation response of these imagers. A significant degradation in quantum efficiency (QE) is observed for thick epitaxial layer at the absorbed dose of 1230 TeV/g. Dark-current damage factor of 0.141 e⁻·s⁻¹·μ m⁻³·(TeV/g)⁻¹ is determined in BSI CIS. The influence of particle types, particle energy, and radiation fluence on dark current distributions is presented at the same displacement damage dose (DDD). Dark current random telegraph signal (DC-RTS) is reported and the variation in epitaxial layer thickness has no influence on DC-RTS behavior. This work highlights the relationship between key parameters and DDD: the limiting factors of the imager performance are single pixel [hot pixel and random telegraph signal (RTS) pixel] at a low DDD range, mean dark current and single pixel at a medium DDD range, and mean dark current in the high DDD case, respectively.

A perturbational method to determine the amplification (attenuation) and velocity of Rayleigh-wave modes in multilayered structures is presented. The perturbation technique, using rigorous analysis as its starting point, is based on the application of the effective permittivity. The computational technique is applied to ZnOSi0,-Si structures. The drifting charge carriers move in an epitaxial layer, which can be partly depleted in order to reduce the dissipation and to control (together with the charge carrier drift velocity) the amplification. The conductivities of the semiconducting layers, the diffusion of charge carriers, the anisotropy, the piezoelectricity and the epitaxial layer thickness and its partial depletion are taken into account in the calculations. the accuracy of the theoretical results are compared with a rigorous analysis. The validity of the computational technique and

This work reports high carrier mobilities and growth rates simultaneously in low unintentionally doped (UID) (1015 cm−3) metalorganic chemical vapor deposition (MOCVD)-grown thick β-Ga2O3 epitaxial drift layers, with thicknesses reaching up to 6.3 μm, using triethylgallium (TEGa) as a precursor. Record-high room temperature Hall mobilities of 187–190 cm2/V s were measured for background carrier density values of 2.4–3.5 × 1015 cm−3 grown at a rate of 2.2 μm/h. A controlled background carrier density scaling from 3.3 × 1016 to 2.4 × 1015 cm−3 is demonstrated, without the use of intentional dopant gases such as silane, by controlling the growth rate and O2/TEGa ratio. Films show smooth surface morphologies of 0.8–3.8 nm RMS roughness for film thicknesses of 1.24–6.3 μm. Vertical Ni Schottky barrier diodes (SBDs) fabricated on UID MOCVD material were compared with those fabricated on hydride vapor phase epitaxy material, revealing superior material and device characteristics. MOCVD SBDs on a 6.3 μm thick epitaxial layer show a uniform charge vs depth profile of ∼ 2.4 × 1015 cm−3, an estimated μdrift of 132 cm2/V s, breakdown voltage (VBR) close to 1.2 kV, and a surface parallel plane field of 2.05 MV/cm without any electric field management—setting record-high parameters for any MOCVD-grown β-Ga2O3 vertical diode to date.