Canonical quaternary signed-digit arithmetic using optoelectronics symbolic substitution

Two-step optoelectronic quaternary signed-digit adder using optical correlation

A hybrid logarithmic processor based on the logarithmic number system (LNS) is introduced The LNS exponents of the operands are represented internally using the signed-digit (SD) number system. The LNS exponents, represented traditionally as fixed-point or sign-magnitude numbers, are converted to an SD format and then processed. This allows the parallelism offered by the SD number system at the digital level to be exploited for the implementation of the various operations. In order to reduce the size of the memory tables required for LNS operations like addition to subtraction, a technique for parallel conversion of SD to sign-magnitude numbers is developed. The new processor compares favorably to a previously developed logarithmic processor in terms of computational speed. It also results in a more regular and modal VLSI implementation. >

Signed-digit number system is an unconventional number system which has been found to cause greater efficacy and efficiency in performing some arithmetic operations. Obviously, it seems interesting to investigate signed-digit number system in wider context, including designing magnitude comparator. Although magnitude comparator is an integral part of every standard arithmetic processor, no significant work on magnitude comparison has been reported yet even for the more propitious categories of signed-digit number system, including canonical signed-digit number system. In this paper, an algorithm for magnitude comparison of canonical signed-digit number system is proposed in terms of comparing the magnitudes and signs of some counterpart portions of the inputs. The proposed algorithm can be immediately implemented at hardware level employing some ordinary logic gates only and in every execution stage of the proposed algorithm, all operations may be completed in a fairly small number of logic levels.KeywordsComputer ArithmeticCanonical Signed-Digit NumberMagnitude ComparisonRecurrence RelationPropagation Delay

By introducing a signed-digit (SD) number arithmetic into a residue number system, arithmetic operations can be performed efficiently. In this paper, a new residue-to-binary conversion algorithm for three-moduli set {22n ? 1, 22n+1 ? 1, 2 n } using the residue SD number addition is proposed. Based on the proposed algorithm, the converter can be designed with only four high-speed SD number adders. The comparison of the proposed converter using SD number arithmetic with the converter using binary arithmetic yields more efficient both in terms of area and time.

In this paper we present constant multiplication architectures for the residue number system (RNS) moduli set {2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> -1, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> , 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> +1} using the signed-digit (SD) representation for recoding the constant operand. The resulting circuits require a small number of partial products, hence, their area and delay is also small.

This work looks at optimizing finite impulse response (FIR) filters from an arithmetic perspective. Since the main two arithmetic operations in the convolution equations are addition and multiplication, they are the targets of the optimization. Therefore, considering carry-propagate-free addition techniques should enhance the addition operation of the filter. The signed-digit number system is utilized to speedup addition in the filter. An alternative carry propagate free fast adder, carry-save adder, is also used here to compare its performance to the signed-digit adder. For multiplication, Booth encoding is used to reduce the number of partial products. The two filters are modeled in VHDL, synthesized and place-and-routed. The filters are deployed on a development board to filter digital images. The resultant hardware is analyzed for speed and logic utilization

This paper presents a high-speed Vedic multiplier based on the Urdhva Tiryagbhyam sutra of Vedic mathematics that incorporates a novel adder based on Quaternary Signed digit number system. Three operations are inherent in multiplication: partial products generation, partial products reduction and addition. A fast adder architecture therefore greatly enhances the speed of the overall process. A Quaternary logic adder architecture is proposed that works on a hybrid of binary and quaternary number systems. A given binary string is first divided into quaternary digits of 2 bits each followed by parallel addition reducing the carry propagation delay. The design doesn't require a radix conversion module as the sum is directly generated in binary using the novel concept of an adjusting bit. The proposed multiplier design is compared with a Vedic multiplier based on multi voltage or multi value logic [MVL], Vedic Multiplier that incorporates a QSD adder with a conversion module for quaternary to binary conversion, Vedic multiplier that uses Carry Select Adder and a commonly used fast multiplication mechanism such as Booth multiplier. All these designs have been developed using Verilog HDL and synthesized by Synopsys Design Compiler. They have been realized using the open source NAN gate 15nm technology library. The proposal shows a maximum of 88.75% speed improvement with respect to Multi Value logic based 128x128 Vedic multiplier while the minimum is 17.47%.

Signed digit number representation limit the carry propagation to one position to the left during the operation of addition and subtraction. Carry-free addition for signed digit number systems is primarily a three-step process. The special case of maximally redundant signed digit number systems leads to more efficient carry-free addition. Conventional Signed Digit Adder is implemented for radix 16 symmetric numbers. A new Speculative Adder is designed which is 10% faster and 22% less area than Conventional SD Adder. The register transfer level (RTL) description is done in verilog and the functionality is verified using Xlinx9.2i.KeywordsRedundant numberssigned digitredundancy indexmaximal redundancy

Carry propagation delay is a big obstacle to improve the addition efficiency in computer system. And the more data bits the operands have, the delay is more serious. As data bits of operand in optical computer can be huge this makes carry delay be very serious. How to decrease or even mitigate carry delay in addition is very important to promote optical computer in numerical computing applications. To improve the addition efficiency, a new method to design and implement optical adder is put forward. Fully considering the relations between the addend and augend based on modified signed-digit (MSD) number system operands, division algorithm is presented. It makes the design and implementation of the adder much easy and feasible. Besides, it also guarantees that no carry delay is introduced in the process of addition. Meanwhile, the architecture of the adder, its implementation as well as the auxiliary electronic circuit are also presented. Experimental results show that the architecture and design of the new MSD adder are correct. It can avoid carry propagation and is much efficient for optical addition operation.

We introduce a novel method for complex number representation. The proposed, redundant complex binary number system (RCBNS) is developed by combining a redundant binary number and a complex number in base (-1+j). Donald (1960) and Walter Penny (1964, 1965) represented complex numbers using base -j and (-1+j) in the classified algorithmic models. A redundant complex binary number system consists of both real and imaginary-radix number systems that form a redundant integer digit set. This system is formed by using complex radix of (-1+j) and a digit set of /spl alpha/=3, where /spl alpha/ assumes a value of -3, -2, -1, 0, 1, 2, 3. The arithmetic operations of complex numbers with this system treat the real and imaginary parts as one unit. The carry-free addition has the advantage of redundancy in number representation in the arithmetic operations. Results of the arithmetic operations are in the RCBNS form. The two methods for conversion from the RCBNS form to the standard binary number form have been presented. The RCBNS reduces the number of steps required to perform complex number arithmetic operations, thus enhancing the speed.

A modular arithmetic circuit using a radix-4 minimum-redundant signed-digit number system is proposed. Any arithmetic circuit can be constructed using a single kind of module with a high degree of parallelism. This modularity is very useful for realizing high-performance semicustom VLSI such as a data-driven arithmetic circuit. The module is composed of an adder, a partial product generator, and a quotient digit generator, which are mainly implemented by multiple-valued bidirectional current-mode circuits. It is easy to design any complex arithmetic circuit using the modules. A performance estimation using SPICE simulation shows that the speed of the proposed arithmetic circuits is comparable to that of the fastest binary circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A novel hybrid number representation is proposed. It includes the two's complement representation and the signed-digit representation as special cases. The hybrid number representations proposed are capable of bounding the maximum length of carry propagation chains during addition to any desired value between 1 and the entire word length. The framework reveals a continuum of number representations between the two extremes of two's complement and signed-digit number systems and allows a unified performance analysis of the entire spectrum of implementations of adders, multipliers and alike. We present several static CMOS implementations of a two-operand adder which employ the proposed representations. We then derive quantitative estimates of area (in terms of the required number of transistors) and the maximum carry propagation delay for such an adder. The analysis clearly illustrates the trade-offs between area and execution time associated with each of the possible representations. We also discuss adder trees for parallel multipliers and show that the proposed representations lead to compact adder trees with fast execution times. In practice, the area available to a designer is often limited. In such cases, the designer can select the particular hybrid representation that yields the most suitable implementation (fastest, lowest power consumption, etc.) while satisfying the area constraint. Similarly, if the worst case delay is predetermined, the designer can select a hybrid representation that minimizes area or power under the delay constraint.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A number system uses a set of digits and sign to represent all the numbers. Different number systems use different amount of digits and sign. To compare the leanness of a number system, the cardinality of the complete set of digits and sign are employed in this work. The 01 binary number system is used by almost all the modern computers. It can represent all the real numbers by two digits 0, 1 and a sign (-), which means its cardinality is 3. Thus, the 01 binary system is not a true binary system. After reviewing all the existing number systems it is found that no true binary system exists for real numbers. All the current binary number systems either don’t have radix 2, or have cardinality 3. In this paper, a true binary system for real numbers, with both radix and cardinality 2, is invented based on the principle of Yin-Yang. Surprisingly, this binary system can not only represent all real numbers without using a sign, but also perform arithmetic and Boolean operations without any problem. Furthermore, due to its radix being 2, this true binary system is compatible with the 01 binary system and many operations are interchangeable between the two systems. It is expected that this true binary system will be applied in the fields of number representation, computer science and cryptography.

Execution of arithmetic operations at a very high speed in real time is the major concern in compute intensive digital signal processing (DSP) algorithms Residue Number Systems are being considered as alternative to binary number system because of their capabilities of performing "carry free" arithmetic operations. However, RNS systems have so far been used to handle integer numbers only. Floating Point RNS arithmetic units have obvious advantages over fixed point multiply &amp; accumulate (MAC) units which are the key units in Digital Signal Processors. Keeping this in view, in this paper, the architecture of a floating point MAC unit is presented.

The use of commercially available 1-bit large-scale integration (LSI) correlator chips whose main function is the correlation of sequences of plus ones and minus ones (rather than zeros and ones) as building blocks in the design of multibit correlators is investigated. A radix-2 number system in which the bit values are +or-1 (no zero) is discussed. The development of a simple conversion algorithm to find the +or-1 representation of a number given in 2's complement is presented. Some of the issues raised by this conversion algorithm are discussed. It is shown that if the analog signal is available, there is a simple step to take before the analog-to-digital conversion in order to improve the overall precision. The construction of multibit correlators based on the +or-1 system is compared to alternative approaches. >