Capacitor voltages balancing method for buck modular DC/DC converter

The modular multilevel converter (MMC) is one of the most promising topologies for high- and medium-voltage applications. However, the conventional MMC relies on large arm inductance and complicated feedback control to maintain submodule (SM) capacitor voltages balanced, which requires a large number of voltage sensors and complicated arm current control loops. In contrast to the conventional perspective, the MMC can be regarded as a derivative from the general multilevel topology based on switched-capacitor (SC) structure. The SC structure endows excellent properties to the MMC, such as minimum or no arm inductor and automatic SM capacitor voltage balancing capability. This MMC with minimum or no arm inductor is named as SC-MMC. Since the arm inductances are very small, the SM capacitor voltages can be balanced automatically. Small stray/parasitic inductance is enough to limit inrush current during SM's switching instants to the rated current level. To unleash the automatic SM capacitor voltage balancing capability of the SC-MMC, a Y-matrix modulation (YMM) has been proposed, which does not require closed loop control or any sensor, has no limitations on the number of SMs, and works for both half-bridge and full-bridge SMs. An unresolved issue of the emerging YMM is that, in the published literature, the existence of the Y matrix with full rank has not been proved theoretically beyond the observation for the SC-MMC when the number of SMs is large. In this paper, an analytical proof of the existence of the full rank Y matrix is provided, which implies the automatic voltage balance of SMs for the MMC with arbitrary number of SMs in each arm. Simulation results using the YMM on a 21-level SC-MMC with minimum arm inductance are provided to verify the voltage balance theory/observation of the SC-MMC using the YMM.

Nowadays, with the vigorous development of smart grids, cascaded H-bridge solid-state transformers (CHB-SST) used in distribution network systems have gradually become an important research hotspot. The multiport CHB-SST serves as the interfacing device to interconnect different grids, which has the functions of bidirectional, power flow control, reactive power compensation, and voltage regulation. However, the power fluctuation of the power cells should be constrained by the large capacitors which in turn worsens the system power density. The second order current in the DC-link side of the CHB-SST will cause the fluctuation of the submodule (SM) capacitor voltage, affecting the capacitance value selection. Therefore, this paper proposes a method to suppress the SM capacitor voltage fluctuation of CHB-SST through fluctuating power control strategy. The control scheme passes the second order current component of the SM capacitor to the low-voltage side of the CHB-SST to reduce the voltage fluctuation of the SM capacitor, such that the capacitance can be optimized. The proposed method is verified via the MATLAB/Simulink model, proving that the fluctuation of the SM capacitor voltage can be effectively suppressed.

This article proposes a method to determine the average submodule (SM) capacitor voltage for reduced current stresses and better total harmonic distortion (THD) of the phase voltages in a flying-capacitor modular multilevel converter (FC-MMC) for medium-voltage ac machine drive systems. Higher ripple is induced in the low-frequency voltage of the SM capacitors by partially alleviating the low-frequency power fluctuation in one half-arm. With this ripple value, the average SM capacitor voltage is determined so that its fluctuations are kept within the limit of the SM capacitor voltage. Consequently, the ac-circulating current amplitude can be decreased with partial alleviation of the low-frequency power fluctuation. Thus, current stresses in switching devices, inductors, and flying capacitors are reduced. In addition, the THD of the phase voltage is improved in low-speed operation. The feasibility of the proposed control strategy has been confirmed through a simulation and experiment.

Low device switching frequency is preferred in high-power converters to achieve higher efficiency, higher device utilization, and feasible cooling system design. However, low device switching frequency operation leads to higher peak voltage in submodule (SM) capacitors of medium-voltage modular multilevel converters (MMC). The main reason is unequal distribution of energy among SMs in each fundamental period due to fewer switching commutations available for balancing. This results in increased converter cost due to higher voltage rating of SM capacitors and semiconductor devices. Therefore, the main objective of this paper is to propose a new SM selection algorithm to reduce the peak voltage of SM capacitors without significantly increasing the device switching frequency. The main idea is to avoid unnecessary switching commutations by ensuring balancing of SM capacitor voltages only at the end of charging period. The proposed algorithm has been verified with extensive simulation studies of a 5L-MMC and it has been observed that peak voltage is kept within 10 % of the nominal value while limiting the device switching frequency in the range of 350 to 400 Hz.

SummaryThe intrinsic characteristics such as modular structure, filterless operation, and absence of DC‐link capacitor have made the modular multilevel converter (MMC) superior to the conventional multilevel converters. However, the submodule (SM) capacitor voltage balancing is crucial. This paper presents a voltage balance control method for MMC. The proposed method generates 2N + 1 levels (where N is the number of SMs per arm) which halves the step size of output voltage and improves the harmonic performance as compared to N + 1 level generation. It requires only one carrier per phase and no voltage and current measurements are needed for the implementation. Therefore, the proposed method makes the system cost‐effective and reduces the implementation issues related with carrier‐based methods substantially. It also alleviates the non‐uniform charge distribution problem with the phase disposition pulse width modulation (PDPWM) technique. Further, a detailed mathematical analysis is presented which enhances the understanding of balancing algorithm. In addition to this, the circulating current with 2N + 1 modulation is analyzed and a control technique is presented. The proposed voltage balancing method is simulated comprehensively in MATLAB/SIMULINK software and validated by the experimental results obtained from a laboratory prototype.

Unlike the modular multilevel converter (MMC) topology operated under the rectifier or inverter modes, control of the balanced state for the submodule (SM) capacitor voltage has emerged as the key issue for DC-DC MMCs. This is mainly caused by no balanced alternative powers being used for balancing SM capacitor voltages, which can be absorbed from the input or output DC sides of the converter. Typically, the alternative voltages and currents should be injected to achieve SM capacitor voltage balance in the DC-DC MMC. However, this solution is based on the cost of adopting the bulky LC filter components. For interconnecting different DC voltages in medium-voltage applications, this paper presents a non-isolated DC-DC MMC equipped with the proposed middle cells. It is intended to achieve DC voltage conversion without adopting bulky passive LC filters. On the one hand, the alternative currents, used for balancing the SM capacitor voltages, are arranged for flowing only within the phase legs of the proposed DC-DC MMC without disturbing the input current. On the other hand, through appropriate control of the middle cells, compensated components can be developed to eliminate the undesirable voltages on the output DC side. The middle cells of the proposed DC-DC MMC are supplied with the function of the active filter, which enables the DC-DC MMC system to escape the bulky LC components. Through theoretical analysis and a control strategy, the proposed DC-DC MMC has been analyzed comprehensively. Finally, the simulation and experimental results are verified to evaluate the effectiveness of the proposed DC-DC MMC.

Summary form only given. The modular multilevel converter (MMC) is a potential candidate for medium/high-power applications, specifically for high-voltage direct current (HVDC) transmission systems. One of the technical challenges associated with the control of an MMC is to carry out the submodule (SM) capacitor voltages balancing task without imposing any unnecessary switching transition among the SMs. This paper develops a general framework for the capacitor voltage balancing of an MMC. Based on the developed framework and with the objective of reducing the unnecessary switching transitions among the SMs, three capacitor voltage-balancing strategies are proposed and investigated: 1) a slow-rate balancing strategy based on the conventional sorting method; 2) a hybrid balancing strategy which combines a predictive method with the conventional sorting method; and 3) a fundamental-frequency balancing strategy. Performance of the proposed strategies for a point-to-point 21-level MMC-based HVDC system is evaluated based on time-domain simulation studies in the PSCAD/EMTDC software environment. The reported study results demonstrate the capability and tradeoffs of the proposed strategies to reduce the number of switching transitions and, consequently, the MMC losses, under various conditions.

Multilevel inverter allows the production of high voltage with lower harmonic distortion in ac output and it eliminates the need of transformer. With the usage of multilevel inverter, we can get the required ac voltage output from multiple dc voltage rails. One of the disadvantage in it is the unbalancing of dc link capacitor voltage. The basic aim of this paper is the balancing of dc link capacitor voltage in diode-clamped multilevel inverter. There are different approaches which could be used for balancing of the capacitor voltage. In this paper, the method of additional auxiliary circuit in the form of Two-level Boost converter is being adopted to balance the inner capacitor voltages so as to get the required multilevel output. This balancing leads to the reliability in the inverter output voltage and extension in life of capacitor. The simulations for this are being performed in MATLAB SIMULINK® and the result are being analyzed for the same by employing it for different load condition. The scheme thus offer the proper balancing of capacitor voltage.

The inherent problem of dc-link capacitor voltage imbalance in multilevel diode-clamped converters limits their development and industrial applications. By using conventional space vector PWM (CSVPWM), for higher voltage levels (>3), the balancing of capacitors voltages cannot be attained under some operational conditions. Virtual vector PWM (VVPWM) assures the balancing of capacitor voltages for all operational conditions with the expense of computation burden by rapid increase in triangular regions for higher levels as compared to CSVPWM. To overcome this problem, this paper presents a simplified virtual vector PWM (SVVPWM) algorithm for four-level diode-clamped converter. The pair of new virtual vectors is defined in such a way that the space vector diagram of four level converter is transformed into three level space vector diagram that reduces the computation burden by decreasing the number of triangular regions. The proposed modulation algorithm guarantees the balancing of middle capacitor voltage in each carrier cycle and the balancing of bottom and top capacitor voltages in a fundamental cycle. The simulation results validate the proposed algorithm under the full range of load power factor and modulation index.

The great number of power modules (PMs) imposes great computational challenge on the voltage balancing of modular multilevel converter (MMC) as the sorting of the PM capacitor voltages is usually adopted. This paper presents a distributed control method for PM capacitor voltage balancing in MMC. With this method, all PMs in one arm are grouped and the sorting algorithm of the voltage balancing in each group is implemented in decentralized control unit. To keep the voltage balancing among different groups, a close-loop control system is proposed, using the average capacitor voltage of each group as the feedback. With this method, the computational load is reduced compared to the conventional method while the voltage balancing effect and the switching frequency are almost the same. Real-time experimental results on a ±350 kV/1000 MW MMC based on RT-LAB (OP7020 and OP5607) verify the feasibility and effectiveness of the proposed method.

To further improve the power supply sustainability of the ac/dc hybrid distribution networks, this article proposes a control strategy for the modular multilevel converter (MMC) under grid-side open-circuit fault, which is based on independent arm current control. Firstly, the behaviors of the MMC after the faults are analyzed, including single-phase and two-phase open-circuit faults. For single-phase open-circuit fault, the proposed strategy can be achieved by reconfiguring the amplitude and phase of the arm currents, thereby eliminating the zero-sequence current. For two-phase open-circuit fault, both the arm currents and voltages need to be reconfigured. After that, a method for detecting and locating specific faults is provided, which can be implemented by detecting the amplitude of the zero-sequence current. Besides, the postfault characteristics of the MMC under single-phase open-circuit condition are given, including submodule (SM) capacitor voltage ripple, circulating current, arm rms current and arm peak current. According to it, long-term postfault operation of the MMC can be guaranteed with 50% of the rated power. Additionally, stable dc-bus voltage and balanced SM capacitor voltage are satisfied even though one phase is disconnected. Moreover, with the proposed control strategy, although the MMC is able to operate for a short period of time in emergency situations when two phases are disconnected, it is not supposed to transmit power due to the inevitable large current on neutral conductors. Finally, the feasibility and effectiveness of the proposed control strategy is validated by simulation and experimental results.

The resonant converter with modular rectifier (RMR) is a promising topology for DC grid applications. This paper studies the control strategy of RMR based SiC switching device including the output voltage and submodule (SM) capacitor voltage balancing control strategy. Firstly, different working modes of the RMR converter are analyzed, and the Critical Mode with the highest efficiency is introduced. A control method is proposed to guarantee the RMR operating the Critical Mode. The control parameters design is detailed. Secondly, the charging and discharging principles of SM capacitor voltages are introduced, then a balancing method is proposed: the SM capacitor voltages are sorted, then assign gate signals with smaller pulse width to SMs with lower capacitor voltages, and vice versa. The proposed control methods are verified by experimental results on a 300 V/1200 V 8 kW RMR prototype based SiC switching device. According to the experimental results, the RMR operates at the Critical Mode under different load and gain conditions. The SM capacitor voltages are well balanced. The peak efficiency is 98.2%.

DC voltage control for modular multilevel converter (MMC) not only needs to control the total DC voltage, but also must control the capacitor voltage balancing of each sub-module (SM). The sorting-based traditional capacitor voltage balancing control algorithm is simple and easy to implement, but it needs to sort the capacitor voltages of all SMs of the valve arm and has low calculation efficiency. In this paper, a novel capacitor voltage balancing control algorithm based on the dynamic tiered sorting is proposed. By dynamically layering all sub-modules (SMs) on the valve arm, the number of SMs participating in the sorting is greatly reduced. Finally, the proposed algorithm is applied to the electromagnetic transient program of ADPSS (Advanced Digital Power System Simulator, ADPSS), and the correctness and the effectiveness of the proposed algorithm are verified by the back-to-back MMC-HVDC simulation case. The results show that the proposed algorithm not only can achieve the same control effect as the traditional algorithm, maintain the stability of all SMs capacitor voltage on the valve arm, but also can greatly improve computational efficiency.

The modular multilevel converter (MMC) has become the most attractive converter technology for medium/high-power applications, specifically for high-voltage dc (HVdc) transmission systems. One of the technical challenges associated with the operation and control of the MMC-based system is to precharge the submodule (SM) capacitors to their nominal voltage during the startup process. In this paper, considering various SM circuits, a generalized precharging strategy is proposed for the MMC-based systems, which can implement soft startup from the dc or ac side. The proposed precharging strategy can be applicable for various SM circuits and MMC configurations. The proposed startup strategy does not require extra measurements and/or auxiliary power supplies. The charging current is controlled by adjusting the changing rate of the number of blocked and bypassed SM capacitors. Based on the proposed startup strategy, the startup processes of MMC/MMC-HVdc systems with various SM circuits are analyzed and a generalized startup procedure for various MMC-HVdc systems is proposed. In addition, the uncontrollable steady-state SM capacitor voltages of various MMC-based systems are analyzed and the associated precharging time is also investigated. Performance of the proposed strategy for various MMC-HVdc systems is evaluated based on time-domain simulation studies in the PSCAD/EMTDC software environment and experimental results are based on a scaled-down prototype.

The modular multilevel converter (MMC) is emerged as the most favourable multilevel converter topology for medium to high-voltage applications. Reliability is one of the major concerns in an MMC due to high fragile component count. Due to low-cost and high energy density, electrolytic capacitors (ECs) are usually preferred as floating capacitors in the MMC. However, the ECs are gradually degraded over the time due to inherent chemical processes, which results in a decrease in capacitance value. This results in an increase in voltage ripple across the SM capacitors and would distort the output waveforms. Moreover, the prolonged use of these aged capacitors could disrupt the MMC operation. Therefore, monitoring and failure detection of submodule (SM) capacitors in an MMC are pivotal to enhance the reliability. This paper presents an SM capacitance estimation strategy for an MMC using nearest level modulation (NLM). A modified voltage balancing control structure with NLM is presented to reduce the unbalance in the capacitor voltages. The proposed approach uses available hardware for converter control with easy implementation in the same controller. Extensive studies are conducted on a three-phase MMC in PLECS simulation platform. Furthermore, experimental results are presented to substantiate the effectiveness of the proposed approach.