CAPE: A cross-layer framework for accurate microprocessor power estimation

Accurate and efficient power estimation at higher-levels of abstraction is becoming increasingly important. However, tools and methodologies are lacking for such a task. In this paper, we present a methodology for accurate power estimation at high-level by reusing pre-existing verification or validation resources in the design flow. This novel methodology enables architectural exploration and design optimization through a framework that exploits the abstraction aspect of high-level designs and the availability aspect of well-established tool flows for RTL designs. Thereby, utilizing the best from both worlds (high-level and low-level) to bring forth a fast and accurate enough solution to a well-known problem in the design of low power embedded systems and SoCs. In this paper, the focus is on how to apply our approach on a deign of reasonable complexity. We present the case study of a power state machine controller that is a critical component of most power-aware embedded systems. The approach uses verification collaterals such as test content, assertions, etc., which are normally built during the verification process of a high-level design to enable power profiling and estimation. The presented methodology is specific to a high-level synthesis and power estimation framework.

This paper introduces GLAAPE, a novel graph learning-assisted neural network model that enables fast, accurate, and transferable estimation of average power in gate-level combinational designs from Register Transfer Level (RTL) simulation. GLAAPE learns to propagate the average toggle rates by effectively embedding the structural information and logical function feature values as vectors on each logic cell of the netlist file. GLAAPE predicts the output toggle rates of combinational logic cells and hence the average power of the benchmark circuits from inputs obtained through RTL simulation without the requirement of gate-level simulation. We evaluate GLAAPE with the commercial gate-level power estimation tool for inference throughput, which is, on average, 15.69X faster. GLAAPE outperforms the commercial RTL Power estimation tool for average power estimation by achieving a mean improvement of 25.28%. We also compare GLAAPE with the state-of-the-art model GRANNITE to predict the output toggle rates to demonstrate the transferability and achieve better accuracy with a mean improvement of 13.95%. We consider a good range of benchmark circuits for analysis, and our experimental results show the generalization and efficacy capability of GLAAPE.

In this work, we propose an electronic system-level (ESL) power estimation framework which can support several low power methodologies such as dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM). Based on the proposed framework, designers can analyze the system power and develop the suitable low power strategies for different applications in the early design stage. The proposed framework had been applied to a heterogeneous multi-core platform. We rapidly characterized the required power models by using physical power measurement to construct the ESL power estimation environment. According to the experimental results, using the proposed framework can have quite accurate power estimation and correct power trend prediction in different voltage/frequency conditions. We also had demonstrated that the low power methodologies can be analyzed and simulated based on this framework.

The paper presents a novel high-level power modeling and estimation framework. The approach is based on a synergic integration of aspect-oriented programming(AOP) and SystemC. Macro module modeling and power estimation are harnessed. A case study demonstrates the effectiveness of the proposed method.

Processor power and energy consumption estimation techniques in IoT applications: A review

In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the observation that most power estimation tools typically perform the following sequence of operations: simulating the circuit to obtain value traces or statistics for the inputs of its constituent components, evaluating power models for each circuit component based on the input values seen during simulation, and aggregating the power consumption of individual components to compute the circuit's power consumption. We further recognize that the steps involved in power estimation (power model evaluation, aggregation) can themselves be thought of as synthesizable functions and implemented as hardware circuits. Thus, any given design can be enhanced by adding to it .power estimation hardware., and the resulting power model enhanced circuit can be mapped onto a hardware prototyping platform. While drastic speedups in power estimation (orders of magnitude) are possible using this approach, a significant challenge arises due to the increase in circuit size as a result of adding power estimation hardware. We propose a systematic methodology to reduce the size of the power model enhanced circuit through a suite of techniques, including power model reuse across different circuit components, regulating the granularity of components for power modeling, exploiting inter-component power correlations, resource sharing for power model computations, and the use of block memories for efficient storage within power models. We demonstrate the benefits of the proposed power emulation paradigm by applying it to register-transfer level (RTL) power estimation for industrial designs, resulting in speedups from around 10X to over 500X compared to state-of-the-art commercial power estimation tools.

Power reduction is nowadays becoming the first consideration in VLSI design. Low power is one of major concerns in deeply scaled CMOS technologies. There have been many methods in very wide rang to achieve this objective. And the Register-Transfer level (RTL) has become the most effective stage in low power VLSI design, according to the significant power optimization impact and accurate power estimation. In this paper, some respective low power design techniques at RTL are re-investigated at tsmc 45 nanometer CMOS technology. Clock gating (CG) is one of the most widely used and effective technique in RTL low power design. Without the enable signal, bus-specific clock gating (BSC) and threshold-based clock gating (TCG) are considered. Also an improved active-driven optimized bus-specific clock gating (OBSC) is proposed in our laboratory. When the enable signal is taken into account, this paper explains local-explicit clock gating (LECG), enhanced clock gating (ECG), waste-toggle-rate-based (WTR) clock gating and the single comparator-based clock gating (SCCG) techniques. Operand isolation is another useful design technique for reducing the power consumption by blocking some redundant operations. Memory splitting is an effective design solution for low power design as well. These techniques have been experimented by using tsmc 45nm technology library and the proposed low-power RTL techniques are evaluated at gate level with logic synthesis results.

We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of glitching activity at various data path and control signals, which can lead to significant underestimation of switching activity. For data path blocks that operate on word-level data, we construct piecewise linear models that capture the variation of output glitching activity and power consumption with various word-level parameters like mean, standard deviation, spatial and temporal correlations, and glitching activity at the block's inputs. For RTL blocks that operate on data that need not have an associated word-level value, we present accurate bit-level modeling techniques for glitching activity as well as power consumption. This allows us to perform accurate power estimation for control-flow intensive circuits, where most of the power consumed is dissipated in non-arithmetic components like multiplexers, registers, vector logic operators, etc. Since the final implementation of the controller is not available during high-level design iterations, we develop techniques that estimate glitching activity at control signals using control expressions and partial delay information. Experiments on example RTL designs resulted in power estimates that were within 7% of those produced by an inhouse power analysis tool on the final gate-level implementation.

We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of glitching activity at various data path and control signals, which can lead to significant underestimation of switching activity. For data path blocks that operate on word-level data, we construct piecewise linear models that capture the variation of output glitching activity and power consumption with various word-level parameters like mean, standard deviation, spatial and temporal correlations, and glitching activity at the block's inputs. For RTL blocks that operate on data that need not have an associated word-level value, we present accurate bit-level modeling techniques for glitching activity as well as power consumption. This allows us to perform accurate power estimation for control-flow intensive circuits, where most of the power consumed is dissipated in non-arithmetic components like multiplexers, registers, vector logic operators, etc. Since the final implementation of the controller is not available during high-level design iterations, we develop techniques that estimate glitching activity at control signals using control expressions and partial delay information. Experiments on example RTL designs resulted in power estimates that were within 7% of those produced by an inhouse power analysis tool on the final gate-level implementation.

Optimizing power dissipation is now a major concern in IC design. Accurate power estimation at the circuit level is too expensive. Tools which estimate power dissipation at higher levels of abstraction without sacrificing accuracy are of interest. We discuss a new cell-library based technique for power estimation. An I/O transition model is developed to represent energy consumption in library elements. Power estimation based on the I/O model requires less computational effort than with previous models. The I/O model also addresses accuracy limitation of previous models. A power estimation tool IOTA, based on this model, has been implemented in C and Matlab. For reasonably large combinational and sequential arithmetic circuits, IOTA has an average error of 5% and low simulation time compared to SPICE simulations.

In VLSI design flow, the designer has better control over critical parameters such as power consumption and delay at higher levels of abstraction. Trade-offs and design changes are easier to accomplish at architectural and system levels. The decisions taken at these levels have a large impact on the final quality of the design. Power consumption has become a vital issue in all modern designs. However, actual information on this important metric is available only after the back-end phase when the design is committed to silicon. At this juncture, very little can be done to optimize power. Therefore, power estimation at higher levels is an extremely crucial step in executing power aware designs. Power estimation techniques can be applied at all abstraction levels in the low power design flow, of which highest level is system level. The design process at higher abstraction level shields the designer's crucial time and effort in power estimation. It is challenging to extract and analyse knowledge about the circuit of the system at the system level. If we estimate the power at this level, large power savings can be done and also power optimized design changes can be done. This paper describes an augmented power estimation methodology for intellectual property (IP) components. The method uses statistical methods to isolate a set of input influencing the output power for a particular mode of operation. The power model is developed as a function of parameters such as signal probability, transition density and spatial correlation. The proposed method was evaluated on a SDRAM controller core. The power estimation error varies from 0.3% to 12.5%.

Fast and accurate power estimation has become an important topic with the increasing need for low power electronics. In this paper we address the problem of using event-driven simulation tools for power estimation. We identify and compare two approaches: input-driven and output-driven, and propose several ways of improvement. The estimation accuracy is degraded in event-driven power estimators due to superfluous and partial glitches. We described glitch filtering and estimation techniques pertaining to input-driven and output-driven power estimators. An output-driven power estimator, Peony, was developed which used the proposed path power idea to improve the estimation accuracy. It achieved significant power estimation accuracy improvement at a speed of two orders of magnitude faster than Spice.

With the evolution of the GSM mobile to a multi-media mobile terminal, optimizing the power consumption becomes an extremely complex task. New operating modes like the MP3 player mode or high resolution graphic games gain significant importance from a power consumption point-of-view. Submicron technologies with their significantly increased leakage currents pose another new challenge. New power concepts are required to achieve reasonable operating and standby times. The design methodology, power estimation and optimization of low power have to be pursued at all stages of the design down to gate level. They also have to be compatible with standard or custom software to minimize the impact on time-to-market for the custom product. This paper mainly talks about the lower power techniques implemented at system/architecture and register transfer level in a complex mix-signal mobile baseband SoC, low-power design optimization flow, power management technique fulfilling mobile application and on-chip low-power memory.

Nowadays, machine learning (ML) algorithms are receiving massive attention in most of the engineering application since it has capability in complex systems modeling using historical data. Estimation of power for CMOS VLSI circuit using various circuit attributes is proposed using passive machine learning-based technique. The proposed method uses supervised learning method, which provides a fast and accurate estimation of power without affecting the accuracy of the system. Power estimation using random forest algorithm is relatively new. Accurate estimation of power of CMOS VLSI circuits is estimated by using random forest model which is optimized and tuned by using multiobjective NSGA-II algorithm. It is inferred from the experimental results testing error varies from 1.4% to 6.8% and in terms of and Mean Square Error is 1.46e-06 in random forest method when compared to BPNN. Statistical estimation like coefficient of determination (R) and Root Mean Square Error (RMSE) are done and it is proven that random Forest is best choice for power estimation of CMOS VLSI circuits with high coefficient of determination of 0.99938, and low RMSE of 0.000116.

Long Term Evolution (LTE) of UMTS Terrestrial Radio Access and Radio Access Network is a Fourth Generation wireless broadband technology which is capable of providing backward compatibility with 2G (Second Generation) and 3G (Third Generation) technologies. LTE is able to deliver high data rate and low latency with reduced cost. It uses the frame structure as Time Division Duplexing (TDD) Land Frequency Division Duplexing (FDD). The broadcast channel in LTE is Physical Broadcast Channel (PBCH) information is divided into two categories one is Master Information Block (MIB) consists of a limited number of the most frequently transmitted parameters essential for initial access to the cell, and is carried on the PBCH and the other System Information Blocks (SIB) at the physical layer are multiplexed together with unicast data transmitted. The main objective of this paper is the realization of receiver architectures for PBCH in LTE considering Single Input Single Output (SISO), Multiple Input Single Output (MISO), Single Input Multi Output (SIMO), and Multiple Input Multiple Output (MIMO). The Receiver processing steps involves as channel de-estimation, demodulation, minimum mean square error (MMSE) and among the received data minimum value is calculated using the comparator at receiver side. By applying the following VLSI DSP methods folding to reduce the number of resource elements required and another method consider to reduce the delay is Super scalar processing method and the results are compared between the direct method, folding method and super scalar method. Based on simulation and implementation, results are discussed in terms of Register Transfer Level (RTL) design, Field Programmable Gate Arrays (FPGA) editor, power estimation and resource estimation. To simulate all the modules of all PBCH channel Verilog code, Modelsim is used. For synthesis and implementation of the above architecture PlanAhead 13.4 tool on Virtex-5, xc5vlx50tff1136-1 device board is used.