- https://doi.org/10.1109/pdgc56933.2022.10053133
Cellular Automata Based Fault Tolerant Test logic for L1 Cache in Tiled CMPs
- Nov 25, 2022
- Mousumi Saha +3 more
The present work focuses on a test design with self correcting features and with much higher efficiency for L1 cache modules. It is based on 2-state 3-neighborhood cellular automata (CA). The design ensures identification of the region of defective cache module in the Chip Multiprocessors (CMPs) and can memorize the fault while continuing with the test. Exploration of 3-neighborhood CA theory further strengthens the design towards a fault tolerant test structure. Self correction of the single stuck-at fault as well as the multiple stuck-at faults in the test structure has been envisaged. This fault tolerant test hardware achieves 100% accuracy in testing for single stuck-at fault whereas, the accuracy for multiple stuck-at faults is found to be 22%. As the design is developed around the 3-neighborhood CA, it becomes simpler as well as cheaper while considering VLSI implementation than that of the 5-neighborhood CA based design proposed in the literature.
- # Fault Tolerant Test
- # Stuck-at Fault
- # Tiled Chip Multiprocessors
- # Multiple Stuck-at Faults
- # Single Stuck-at Fault
- # Cellular Automata
- # Cache Module
- # Chip Multiprocessors
- # Cache In Chip Multiprocessors
- # Multiple Faults
