Channel routing with short wires

In the routing design of interposer and etc., the combination of a pin pair to be connected by wire is often flexible, and the reductions of the total wire length and the length difference are pursued to keep the circuit performance. Even though the total wire length can be minimized by finding a minimum cost maximum flow in set pair routing problems, the length difference is often large, and the reduction of it is not easy. In this paper, an algorithm that reduces the length difference while keeping the total wire length small is proposed. In the proposed algorithm, an initial routing first obtained by a minimum cost maximum flow. Then it is modified to reduce the maximum length while keeping the minimum total wire length, and a connection of the minimum length is detoured to reduce the length difference. The effectiveness of the proposed algorithm is confirmed by experiments.

Fixed-die floorplanning is an important problem in the modern physical design process. An effective floorplanning algorithm is crucial to improving both the quality and the time-to-market of the design. In this paper, we present an analytical floorplanning algorithm that can be used to efficiently pack soft modules into a fixed die. The locations and sizing of the modules are simultaneously optimized so that a minimum total wire length is achieved. Experiments on the MCNC and GSRC benchmarks show that our algorithm can achieve above a 90% success rate with a 10% white space constraint in the fixed die, and the efficiency is much higher than that of the simulated annealing based algorithms for benchmarks containing a large number of modules.

River routing in VLSI

3D channel routing is a fundamental problem in the physical design of 3D integrated circuits. The 3D channel is a 3D grid G and the terminals are vertices of G located in the top and bottom layers. A net is a set of terminals to be connected. The object of the 3D channel routing problem is to connect the terminals in each net with a tree (wire) in G using as few layers as possible and as short wires as possible in such a way that wires for distinct nets are disjoint. This paper shows that any set of n 2-terminal nets can be routed in a 3D channel with O(/spl radic/n) layers using wires of length O(/spl radic/n). We also show that there exists a set of n 2-terminal nets that requires a 3D channel with /spl Omega/(/spl radic/n) layers to be routed.

Minimizing the total length has been one of the main optimality criteria for triangulations and other kinds of partitions. Indeed, the minimum weight triangulation or MWT (i.e. a triangulation of minimum total edge length) has frequently been referred to as the optimal This triangulation has some good properties [1] and is e.g. useful in numerical approximation of bivariate data [23]. Its complexity is one of the most intriguing problems in computational geometry. No proof has yet been presented showing that it is NP-hard. On the other hand, no polynomial time heuristic for it was shown to guarantee even a constant approximation factor. However, very recently we proved that what we called the quasi-greedy triangulation has length within a constant factor from the minimum [13]. A standard implementation of that heuristic using known results would yield a quadratic time algorithm. In this paper, we improve on this by describing an O(n log n) algorithm for quasi-greedy triangulation. Moreover, if the Delaunay triangulation is given, our algorithm runs in linear time. The minimum weight convex partition (MWCP) problem has been shown to be NP-complete [7, 17]. By a MWCP we mean a set of non-crossing diagonals (i.e. without Steiner points) of minimum total length which includes the convex hull and partitions it into empty convex polygons. In [13] it was shown that, given the quasi-greedy triangulation, a convex partition of length within a constant factor from the MWCP can be computed in linear time. Thus from the results in this paper we also obtain a fast heuristic for approximating the MWCP. The quasi-greedy triangulation is very closely related to the greedy triangulation (both are defined in the next section). In fact, we will describe an algorithm that, given the Delannay triangulation, computes the greedy triangulation in linear time. This algorithm behaves in such a way that it is very easily adapted to yield an algorithm for the quasi-greedy triangulation. Consequently, we also present the first O(n log n) algorithm for greedy triangulation. (By using a substantially different approach, an attempt to develop an O(n log n) algorithm for greedy triangulation was done in [21]. Even if that approach could be corrected

Channel routing problem of area minimization is a well-defined problem in VLSI physical design automation. In this paper we have developed algorithms for computing reduced wire length channel routing solutions using a purely graph theoretic framework, TAH (track assignment heuristic) that was designed for computing minimum area routing solutions. Here we consider the total wire length of a routing solution as one of the most important factors of high performance computing. Reduction in wire length is important from signal delay as well as from the viewpoint of cost of wire segments required in interconnecting all the nets. The framework is designed for computing routing solutions in two-layer channels, and extended to route three-layer routing also in a modular fashion. All the algorithms developed under the framework of TAH are executed for computing no-dogleg and dogleg routing solutions for most of the well-known benchmark channels, with reduced total area and/or total wire length in two- and three-layer channel routing. Performance of our algorithms is highly encouraging.

The first stage in channel routing is that of computing a routing solution S, for a given channel with as few tracks as possible. We consider a second stage in which it is desirable to reduce the total wire length without increasing area of routing. In this paper we propose efficient polynomial time algorithms for appreciably reducing the total wire length in two-, three- and multi-layer routing solutions by permuting tracks in the solution S obtained in the first stage. This results in a routing solution that is economical in terms of area as well as total wire length. Our algorithms are particularly important in practical terms since the problem of minimizing the total wire length in a routing solution is NP-hard.

In this paper we have developed algorithms for generating random channel instances for their use in computing channel routing solutions in VLSI physical design. Channel instances are usually of two types: simple and general, and there are usually two kinds of inherent constraints involving channel routing problem: horizontal constraint and vertical constraint. Simple channel instances do not contain any vertical constraint, whereas, general channel instances contain both horizontal as well as vertical constraints. Most of the optimization problems in two-, three-, and multi-layer channel routing are NP-hard and, in fact, very few are polynomial time computable. Hence for each of the NP-hard problems in channel routing, it is unlikely to design a polynomial time deterministic algorithm. Developing heuristic algorithm may be a probable way out that hopefully provides good solutions for most of the instances available in literature. Novelty of a heuristic algorithm is judged better if it works for a variety of large number of randomly generated instances of the problem.

As the very large scale integration (VLSI) technology approaches its fundamental scaling limit at about 0.2 /spl mu/m, it is reasonable to consider three-dimensional (3-D) integration to enhance packing density and speed performance. With additional functional units packed into one chip in a 3-D space, computer-aided design (CAD) tools are demanded to ease the complicated design work. This paper presents a 100% completion achievable routing methodology. The routing methodology is based on the two-dimensional (2D) channel routing methodology; thus, it is called a 3-D channel routing methodology. With the routing methodology, a 3-D routing problem is decomposed into two 2D routing subproblems: intra-layer routing that interconnects terminals on the same layer, which can be done by using a 2-D channel router, and inter-layer routing that interconnects terminals on different layers. The inter-layer routing problem is transformed into a 2-D channel routing problem and the transformation is made in some 3-D channels. Detailed discussions are given for the 3-D to 2-D transformation. Optimization of the transformation is shown to be NP-complete. Thus, simulated annealing is used to optimize the transformation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Wireless mesh networks are being deployed all around the world both to provide ubiquitous connection to the Internet and to carry data generated by several services (video surveillance, smart grids, earthquake early warning systems, etc.). In those cases where fixed power connections are not available, mesh nodes operate by harvesting ambient energy (e.g., solar or wind power) and hence they can count on a limited and time-varying amount of power to accomplish their functions. Since we consider mesh nodes equipped with multiple radios, power savings and network performance can be maximized by properly routing flows, assigning channels to radios and identifying nodes/radios that can be turned off . Thus, the problem we address is a joint channel assignment and routing problem with additional constraints on the node power consumption, which is NP-complete. In this paper, we propose a heuristic, named minimum power channel assignment and routing algorithm (MP-CARA), which is guaranteed to return a local optimum for this problem. Based on a theoretical analysis that we present in the paper, which gives an upper bound on the outage probability as a function of the constraint on power consumption, we can guarantee that the probability that a node runs out of power with MP-CARA falls below a desired threshold. The performance of MP-CARA is assessed by means of an extensive simulation study aiming to compare the solutions returned by MP-CARA to those found by other heuristics proposed in the literature.

The authors propose a provably good performance-driven global routing algorithm for both cell-based and building block design. The approach is based on a new bounded-radius minimum routing free formulation, which simultaneously minimizes both routing cost and the longest interconnection path, so that both are bounded by small constant factors away from optimal. The authors' method generalizes to Steiner global routing in arbitrary weighted graphs, and to the case where varying wirelength bounds are prescribed for different source-sink paths. Extensive simulations confirmed that the approach gave very good performance, and exhibited a smooth tradeoff between the competing requirements of minimum delay and minimum total wirelength.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Due to the ever-increasing density and complexity of integrated circuits, FPGA prototyping has become a necessary part of the design process. To enhance observability into these devices, designers commonly insert trace-buffers to record and expose the values on a small subset of internal signals during live operation to help root-cause errors. For dense designs, routing congestion will restrict the number of signals that can be connected to these trace-buffers. In this work, we apply optimal network flow graph algorithms, a well studied technique, to the problem of transporting circuit signals to embedded trace-buffers for observation. Specifically, we apply a minimum cost maximum flow algorithm to gain maximum signal observability with minimum total wirelength. We showcase our techniques on both theoretical FPGA architectures using VPR, and with a Xilinx Virtex6 device, finding that for the latter, over 99.6% of all spare RAM inputs can be reclaimed for tracing across four large benchmarks.

We present an algorithm to find a set of all optimal solutions for a channel placement problem. A channel consists of two rows of horizontal line segments (representing components). Each line segment contains some terminals with fixed positions. Sets of terminals, called nets, are to be connected. The relative ordering of line segments in each row is fixed. The line segments can be shifted left or right, which will affect the width needed for routing and the length of the channel. We want to find the tradeoff between channel length and routing width. Since the channel routing problem is NP-complete, we use a lower bound on routing width, called density. The density of a placement is the maximum number of nets crossing each vertical cut. We can increase the total length to minimize the channel density, or minimize the total length by increasing the channel density. The pair (density, total length) is called the shape of a placement. A shape is minimal if a decrease in density would cause an increase in total length, and vice versa. Our algorithm computes all the minimal shapes in O (N 4 ) time, where N is the number of nets. This is the first known algorithm for this problem whose running time is polynomial in the number of nets and independent of the length of the channel.

A branch-and-price algorithm for the Steiner tree packing problem

For multi-radio multi-channel wireless mesh networks (WMNs), the joint channel assignment and routing problem has been shown to be NP-complete. In this paper, we first use a rate-variable model to increase the network through output, which use the physical interference model that can evaluate the capacity more precisely. Then we present a mathematical programming model which allows us to formulate the task of deriving joint channel assignment and routing as an integer linear programming problem. Simulation results show that the proposed approach effectively increases the network through output.